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Chapter 3: XST Hardware Description Language (HDL) Coding Techniques
To insert pipeline stages:
1.
Describe the necessary registers in your Hardware Description Language (HDL) code
2.
Place them after any distributed RAM
3.
Set the RAM Style (RAM_STYLE) constraint to pipe_distributed
In order to reach the maximum distributed RAM speed, XST uses the maximum number of available registers
when:
•
It detects valid registers for pipelining, and
•
RAM _STYLE is set to pipe_distributed
In order to obtain the best frequency, XST automatically calculates the maximum number of registers for each
RAM.
During the Advanced HDL Synthesis step, the XST HDL Advisor advises you to specify the optimum number of
register stages if:
•
You have not specified sufficient register stages, and
•
RAM _STYLE is coded directly on a signal
XST implements the unused stages as shift registers if:
•
The number of registers placed after the multiplier exceeds the maximum required, and
•
Shift register extraction is activated
XST cannot pipeline RAM if registers contain asynchronous set/reset signals. XST can pipeline RAM if registers
contain synchronous reset signals.
XST User Guide
UG627 (v 11.3) September 16, 2009
www.xilinx.com
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