Download Using the Electric VLSI Design System

Chapter 9: Tools
9−5−4: ALS Gates
The gate entity is the primary method of specifying behavior. It uses a truth−table to define the operational
characteristics of a logic gate. Many behavioral descriptions need contain only a gate entity to be complete.
The gate entity is headed by the gate declaration statement and is followed by a body of information. The
gate declaration contains a name and a list of exported simulation nodes (which are referenced in a higher
level model description). The format of this statement is shown below:
Format:
Example:
gate name(signal1, signal2, signal3, ... signalN)
gate nor2(in1, in2, out)
gate and3(a, b, c, output)
There is no limit on the number of signal names that can be placed in the list. If there is not enough room on
a single line to accommodate all the names, simply continue the list on the next line.
The i: and o: Statements (Input and Output)
The i: and o: statements are used to construct a logical truth table for a gate primitive. The signal names and
logical assertions which follow the i: statement represent one of many possible input conditions. If the logic
states of all the input signals match the conditions specified in the i: statement, the simulator will schedule
the outputs for updating (as specified in the corresponding o: statement). The logical truth table for a two
input AND gate is shown below:
gate and2(in1, in2, output)
i: in1=H in2=H o: output=H
i: in1=L o: output=L
i: in2=L o: output=L
i: o: output=X
The last line of the truth table represents a default condition in the event that none of the previous conditions
are valid (e.g. in1=H and in2=X). It should be noted that the simulator examines the input conditions in the
order that they appear in the truth table. If a valid input condition is found, the simulator schedules the
corresponding output assignments and terminates the truth table search immediately.
Using the Electric VLSI Design System, version 9.04
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