Download NGMP baseline design - ESA Microelectronics Section

AEROFLEX GAISLER
331
LEON4-NGMP-DRAFT
Table 395. SPI controller Event register
Overrun (OV) - This bit gets set when the receive queue is full and the core receives new data. The
core continues communicating over the SPI bus but discards the new data. This bit is cleared by writing ‘1’, writes of ‘0’ have no effect.
12
11
Underrun (UN) - This bit is only set when the core is operating in slave mode. The bit is set if the
core’s transmit queue is empty when a master initiates a transfer. When this happens the core will
respond with a word where all bits are set to ‘1’. This bit is cleared by writing ‘1’, writes of ‘0’ have
no effect.
10
Multiple-master error (MME) - This bit is set when the core is operating in master mode and the
SPISEL input goes active. In addition to setting this bit the core will be disabled. This bit is cleared
by writing ‘1’, writes of ‘0’ have no effect.
9
Not empty (NE) - This bit is set when the receive queue contains one or more elements. It is cleared
automatically by the core, writes have no effect.
8
Not full (NF) - This bit is set when the transmit queue has room for one or more words. It is cleared
automatically by the core when the queue is full, writes have no effect.
7:0
RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility.
Table 396. SPI controller Mask register
31
30
15
TIPE
R
14
13
12
11
10
9
8
LTE
R
OVE
UNE
MMEE
NEE
NFE
7
0
R
31
Transfer in progress enable (TIPE) - When this bit is set the core will generate an interrupt when the
TIP bit in the Event register transitions from ‘0’ to ‘1’.
30 : 15
RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility.
14
Last character enable (LTE) - When this bit is set the core will generate an interrupt when the LT bit
in the Event register transitions from ‘0’ to ‘1’.
13
RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility.
12
Overrun enable (OVE) - When this bit is set the core will generate an interrupt when the OV bit in
the Event register transitions from ‘0’ to ‘1’.
11
Underrun enable (UNE) - When this bit is set the core will generate an interrupt when the UN bit in
the Event register transitions from ‘0’ to ‘1’.
10
Multiple-master error enable (MMEE) - When this bit is set the core will generate an interrupt when
the MME bit in the Event register transitions from ‘0’ to ‘1’.
9
Not empty enable (NEE) - When this bit is set the core will generate an interrupt when the NE bit in
the Event register transitions from ‘0’ to ‘1’.
8
Not full enable (NFE) - When this bit is set the core will generate an interrupt when the NF bit in the
Event register transitions from ‘0’ to ‘1’.
7:0
RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility.
Table 397. SPI controller Command register
31
23
R
22
LST
21
0
R
31 : 23
RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility.
22
Last (LST) - After this bit has been written to ‘1’ the core will set the Event register bit LT when a
character has been transmitted and the transmit queue is empty. If the core is operating in 3-wire
mode the Event register bit is set when the whole transfer has completed. This bit is automatically
cleared when the Event register bit has been set and is always read as zero.
21 : 0
RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility.
Copyright Aeroflex Gaisler AB
ESA contract: 22279/09/NL/JK Deliverable: D9
May 2013, Version: Draft-2.1