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Download MCF5329 - Reference Manual
Transcript
Pulse-Width Modulation (PWM) Module PCLR0 1 Clock to PWM0 0 1 Clock to PWM1 0 PCLR1 Clock SA PWMSCLA PCLR4 1 ÷2 Clock to PWM4 0 PWMPRCLK [PCKA] 1 Clock to PWM5 0 Clock A PCLR5 PCLR2 Internal Bus Clock (fsys/3) Clock SB 1 PWMSCLB ÷2 Clock to PWM2 0 PWMPRCLK [PCKB] 1 Clock to PWM3 0 Clock B PCLR3 PCLR6 1 0 1 0 Clock to PWM6 Clock to PWM7 PCLR7 Figure 26-14. PWM Clock Select Block Diagram 26.3.1.1 Prescaled Clock (A or B) The internal bus clock is the input clock to the PWM prescaler that can be disabled when the device is in debug mode by setting the PWMCTL[PFRZ] bit. This is useful for reducing power consumption and for emulation to freeze the PWM. The input clock is also disabled when all PWM channels are disabled (PWMEn=0). Clock A and B are scaled values of the input clock. The value is software selectable for clock A and B and has options of 1, 1/2,..., or 1/128 times the internal bus clock. The value selected for clock A and B is determined by the PWMPRCLK[PCKAn] and PWMPRCLK[PCKBn] bits. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 26-13
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