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Download MCF5329 - Reference Manual
Transcript
Register Memory Map Quick Reference NOTE Debug control registers can be written by the external development system or the CPU through the WDEBUG instruction. CSR is write-only from the programming model. It can be read or written through the BDM port using the RDMREG and WDMREG commands. Table A-6. SCM Memory Map Address Register Width (bits) Access Reset Value Section/Page 0xEC00_00001 Master Privilege Register 1 (MPR1) 32 R/W 0x7000_0007 11.2.1/11-3 0xEC00_00541 32 R/W 0x0000_0008 11.2.4/11-7 0xFC00_0000 Master Privilege Register 0 (MPR0) 32 R/W 0x7777_7777 11.2.1/11-3 0xFC00_0020 Peripheral Access Control Register A (PACRA) 32 R/W 0x5444_4444 11.2.3/11-4 0xFC00_0024 Peripheral Access Control Register B (PACRB) 32 R/W 0x4444_4444 11.2.3/11-4 0xFC00_0028 Peripheral Access Control Register C (PACRC) 32 R/W 0x4444_4444 11.2.3/11-4 0xFC00_002C Peripheral Access Control Register D (PACRD) 32 R/W 0x4444_4444 11.2.3/11-4 0xFC00_0040 Peripheral Access Control Register E (PACRE) 32 R/W 0x4444_4444 11.2.3/11-4 0xFC00_0044 Peripheral Access Control Register F (PACRF) 32 R/W 0x4444_4444 11.2.3/11-4 0xFC00_0048 Peripheral Access Control Register G (PACRG) 32 R/W 0x4444_4444 11.2.3/11-4 0xEC00_00401 Peripheral Access Control Register H (PACRH) 32 R/W 0x4444_4444 11.2.3/11-4 0xFC00_0054 Bus Monitor Timeout 0 (BMT0) 32 R/W 0x0000_0008 11.2.4/11-7 0xFC04_0013 Wakeup Control Register (WCR)2 8 R/W 0x00 8.2.1/8-2 0xFC04_0016 Core Watchdog Control Register (CWCR) 16 R/W 0x0000 11.2.5/11-8 0xFC04_001B Core Watchdog Service Register (CWSR) 8 R/W Undefined 11.2.6/11-9 0xFC04_001F SCM Interrupt Status Register (SCMISR) 8 R/W 0x00 11.2.7/11-10 0xFC04_0024 Burst Configuration Register (BCR) 32 R/W 0x0000_0000 11.2.8/11-10 0xFC04_0070 Core Fault Address Register (CFADR) 32 R 0x0000_0000 11.2.9/11-11 0xFC04_0075 Core Fault Interrupt Enable Register (CFIER) 8 R/W 0x00 11.2.10/11-12 0xFC04_0076 Core Fault Location Register (CFLOC) 8 R Undefined 11.2.11/11-12 0xFC04_0077 Core Fault Attributes Register (CFATR) 8 R Undefined 11.2.12/11-12 0xFC04_007C Core Fault Data Register (CFDTR) 32 R Undefined 11.2.13/11-13 1 2 Bus Monitor Timeout 1 (BMT1) Take note of register location. The WCR register is described in Chapter 8, “Power Management.” MCF5329 Reference Manual, Rev 3 Freescale Semiconductor A-5
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