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ASM Chart Editor
Editing ASM Object Properties
The editable objects are shown in the left pane of the dialog box. Objects which exist in the
current selection set are highlighted in yellow. Objects that are not available in the current
selection are shown in dimmed font.
Editing Clock Object Properties
The Clock page of the ASM Object Properties dialog box allows you to specify the clock signal
and set the clock edge sensitivity.
You can choose the clock signal name from a dropdown list of available input signals. Note that
any signals starting with clk or clock take precedence in the list. For a Verilog view, you can
choose Rising or Falling representing posedge or negedge sensitivity. For a VHDL view, you
can choose Rising, Falling, Rising Last, Falling Last, Rising Edge or Falling Edge. These
options generate the following VHDL expressions:
Rising
Falling
Rising Last
Falling Last
Rising Edge
Falling Edge
clk'EVENT AND clk = '1'
clk'EVENT AND clk = '0'
clk'EVENT AND clk = '1' AND clk'LAST_VALUE = '0'
clk'EVENT AND clk = '0' AND clk'LAST_VALUE = '1'
rising_edge(clk)
falling_edge(clk)
Tip: Note that the clock edge is indicated by a rising or falling waveform on the clock
point icon.
Alternatively for either language, you can choose Specify to enter any other valid edge
condition.
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State Machine Editors User Manual, V2008.1
September 18, 2008