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GAISLER 2 1 Introduction 1.1 Overview LEON3 / LEON3-FT The LEON3 SPARC V8 processor core has been designed to fit into architectures from which a large variety of applications can be derived. The LEON3 SPARC V8 processor core can be combined with the IEEE-STD-754 compliant Floating Point Unit (GRFPU Lite). The architecture is centered around the AMBA Advanced High-speed Bus (AHB), to which the LEON3 core and other high-bandwidth units are connected. Low-bandwidth units connected to the AMBA Advanced Peripheral Bus (APB) which is accessed through an AHB to APB bridge. The architecture is shown in figure 1. LEON3FT 32-bit SPARC Integer Unit I-cache D-cache Interrupt FPU Debug Support Unit UART Debug Link JTAG Debug Link On-Chip Memory with EDAC Timers 2 x UART 16 x GPIO AHB / APB 32-bit AMBA AHB AHB CTRL Memory Controller with EDAC 32 PROM/SRAM SDRAM Controller with EDAC SpaceWire Codec Interface CAN 2.0 Controller LVDS I/F CAN-2.0 Mil-Std-1553 BC/RT/MT Interface Mil-Std-1553 RT Interface Dual-1553 Dual-1553 32 SDRAM Figure 1. Architectural block diagram of a typical system using the LEON3 processor Copyright Aeroflex Gaisler AB March 2010, Version 1.1
