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GAISLER 1.2 3 LEON3 / LEON3-FT Signal overview The LEON3 signals are shown in figure 2. Note that the AMBA AHB and debug signals are implemented VHDL records and are not shown in detail. clk Clock & Reset rstn irqi.irl[3:0] irqo.irl[3:0] Interrupt irqi.rst irqo.intack irqi.run dbgi dbgo Debug ahbi ahbo AMBA ahbsi Figure 2. Signal overview 1.3 Implementation characteristics The LEON3 processor is inherently portable and can be implemented on most FPGA and ASIC technologies. Table 1 shows the approximate cell count and frequency for different example configurations on Actel RTAX and RT ProASIC3, with 8 kbyte instruction and 4 kbyte data caches. Table 1. Implementation characteristics (Cells / RAM blocks / AHB MHz) Core configuration LEON3 LEON3 + GRFPU Lite LEON3-FT LEON3-FT + GRFPU-FT Lite RTAX2000S-1 RT ProASIC3 RT ProASIC3 with TMR 6500 / 31 / 25 MHz - - 13500 / 35 / 20 MHz - - 7500 / 31 / 25 MHz 8400 / 39 / 25 MHz 12300 / 39 / 25 MHz 14600 / 35 / 20 MHz 18200 / 47 / 20 MHz 24800 / 47 / 20 MHz The LEON3 core is available in VHDL source code or as a pre-synthesized netlist. The LEON3-FT core is available as a pre-synthesized netlist only. Copyright Aeroflex Gaisler AB March 2010, Version 1.1
