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FlexBus Table 17-7. Bus Cycle States (continued) State Cycle Description S1 All FB_TS is negated on the rising edge of FB_CLK, and FB_CSn is asserted. Data is driven on FB_D[31:X] for writes, and FB_D[31:X] is tristated for reads. Address continues to be driven on the FB_A pins. If FB_TA is recognized asserted, then the cycle moves on to S2. If FB_TA is not asserted internally or externally, then the S1 state continues to repeat. S2 S3 17.4.5 Read Data is driven by the external device before the next rising edge of FB_CLK (the rising edge that begins S2) with FB_TA asserted. All For internal termination, FB_CSn is negated and the internal system bus transfer is completed. For external termination, the external device should negate FB_TA, and the FB_CSn chip select negates after the rising edge of FB_CLK at the end of S2. Read The processor latches data on the rising clock edge entering S2. The external device can stop driving data after this edge. However, data can be driven until the end of S3 or any additional address hold cycles. All Address, data, and FB_R/W go invalid off the rising edge of FB_CLK at the beginning of S3, terminating the read or write cycle. FlexBus Timing Examples NOTE Because this device shares the FlexBus signals with the SDRAM controller, all signals, except the chip selects, tristate between bus cycles. 17.4.5.1 Basic Read Bus Cycle During a read cycle, the ColdFire device receives data from memory or a peripheral device. Figure 17-7 is a read cycle flowchart. MCF5373 Reference Manual, Rev 3 Freescale Semiconductor 17-13
