1
Download MCF5373 Reference Manual
Transcript
Debug Module Command Sequence: RDMREG ??? XXX MS RESULT NEXT CMD LS RESULT XXX ’ILLEGAL’ NEXT CMD ’NOT READY’ Figure 35-40. RDMREG Command Sequence Operand Data: Result Data: None The contents of the selected debug register are returned as a longword value. The data is returned most-significant word first. 35.4.1.5.15 Write Debug Module Register (WDMREG) The operand (longword) data is written to the specified debug module register. All 32 bits of the register are altered by the write. DSCLK must be inactive while the debug module register writes from the CPU accesses are performed using the WDEBUG instruction. Command Format: Figure 35-41. WDMREG BDM Command Format 15 14 13 12 0x2 11 10 9 8 7 0xC 6 5 4 3 100 2 1 0 DRc D[31:16] D[15:0] Table 35-3 shows the definition of the DRc write encoding. Command Sequence: WDMREG ??? MS DATA ’NOT READY’ LS DATA ’NOT READY’ XXX ’ILLEGAL’ NEXT CMD ’NOT READY’ NEXT CMD ’CMD COMPLETE’ Figure 35-42. WDMREG Command Sequence Operand Data: Result Data: Longword data is written into the specified debug register. The data is supplied most-significant word first. Command complete status (0xFFFF) is returned when register write is complete. MCF5373 Reference Manual, Rev 3 Freescale Semiconductor 35-37
