1
Download MCF5373 Reference Manual
Transcript
Chip Configuration Module (CCM) user may choose to increase these frequencies (240 MHz and 80 MHz) by placing the device in limp mode and reconfiguring the appropriate PLL registers, or asserting D1 during reset configuration. 9.4.3 Oscillator Mode Selection Use of the internal oscillator can be selected during reset configuration via the D2 pin. By default, the oscillator is enabled and the PLL is placed in normal mode with a crystal reference. If default configuration is over-ridden and D2 is asserted, the PLL is placed in normal mode with a external reference and the internal oscillator is bypassed. After reset is exited, the oscillator mode cannot be changed. See Chapter 7, “Clock Module” for more details on the available modes. 9.4.4 Boot Device Selection During reset configuration, the FB_CS0 chip select pin is configured to select an external boot device. In this case, the V (valid) bit in the CSMR0 register is ignored, and FB_CS0 is enabled after reset. FB_CS0 is asserted for the initial boot fetch accessed from address 0x0000_0000 for the stack pointer and address 0x0000_0004 for the program counter (PC). It is assumed that the reset vector loaded from address 0x0000_0004 causes the core to start executing from external memory space decoded by FB_CS0. 9.4.5 Output Pad Strength Configuration Output pad strength is determined during reset configuration as shown in Table 9-11. After reset is exited, the output pad strength configuration can only be changed using the GPIO module. For more information see Chapter 13, “General Purpose I/O Module.” Table 9-11. Output Pad Driver Strength Selection1 Optional Pin Function Selection Output pads configured for low drive strength D5 driven low Output pads configured for full drive strength D5 driven high 1 9.4.6 D5 Modifying the default configurations is possible only if the external RCON pin is asserted low. Chip Select Configuration The chip select configuration (FB_CS[5:4]) is selected during reset and reflected in the CCR[CSC] field. After reset is exited, the chip select configuration cannot be changed. Table 9-10 shows the different chip select configurations that can be implemented during reset configuration. MCF5373 Reference Manual, Rev 3 Freescale Semiconductor 9-11
