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12
Global Timing Constraints
Global timing variables, similar to other global variables, apply to the present design in
memory. Explicitly defined timing constraints override global constraints. Setting these
variables saves considerable time and effort when performing bottom-up optimizations.
Refer to Figure 12-8.
Figure 12-8 Global Timing Constraints
register2output
input2register
regis ter2regis ter
input2output
Hint: Set the input2register and register2output variables to one-half of
the clock period. This ensures that the boundary logic of subblocks meets timing when
combined into the top-level design.
set register2register 20
set input2register 10
set register2output 10
set input2output 10
Resets
Sequential element set and reset pins are automatically blocked during timing analysis.
No special settings or constraints are required to block reset timing paths.
Clocks
LeonardoSpectrum supports one or more synchronous clocks. However, multiple
asynchronous clocks are not supported.
Design Methodology
12-29