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EPIC Register Summary
Table 11-2. EPIC Register Address Map—Global and Timer Registers (Continued)
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Address Offset
from EUMBBAR
Register Name
Field Mnemonics
0x4_1170
Global timer 1 destination register (GTDR1)
P0
0x4_1180
Global timer 2 current count register (GTCCR2)
T (toggle), COUNT
0x4_1190
Global timer 2 base count register (GTBCR2)
CI, BASE_COUNT
0x4_11A0
Global timer 2 vector/priority register (GTVPR2)
M, A, PRIORITY, VECTOR
0x4_11B0
Global timer 2 destination register (GTDR2)
P0
0x4_11C0
Global timer 3 current count register (GTCCR3)
T (toggle), COUNT
0x4_11D0
Global timer 3 base count register (GTBCR3)
CI, BASE_COUNT
0x4_11E0
Global timer 3 vector/priority register (GTVPR3)
M, A, PRIORITY, VECTOR
0x4_11F0
Global timer 3 destination register (GTDR3)
P0
0x4_1200–0x5_01F0
Reserved
—
Table 11-3 defines the address map for the interrupt source configuration registers. Note
that the address space 0x5_0200 through 0x5_0290 maps to the direct interrupt registers or
the serial interrupt registers, depending on the setting of EICR[SIE].
Table 11-3. EPIC Register Address Map—Interrupt Source
Configuration Registers
Address Offset
from EUMBBAR
Register Name
Field Mnemonics
0x5_0200
IRQ0 vector/priority register (IVPR0)
M, A, P, S, PRIORITY, VECTOR
0x5_0210
IRQ0 destination register (IDR0)
P0
0x5_0220
IRQ1 vector/priority register (IVPR1)
M, A, P, S, PRIORITY, VECTOR
0x5_0230
IRQ1 destination (IDR1)
P0
0x5_0240
IRQ2 vector/priority register (IVPR2)
M, A, P, S, PRIORITY, VECTOR
0x5_0250
IRQ2 destination (IDR2)
P0
0x5_0260
IRQ3 vector/priority register (IVPR3)
M, A, P, S, PRIORITY, VECTOR
0x5_0270
IRQ3 destination (IDR3)
P0
0x5_0280
IRQ4 vector/priority register (IVPR4)
M, A, P, S, PRIORITY, VECTOR
0x5_0290
IRQ4 destination (IDR4)
P0
0x5_0200
Serial interrupt 0 vector/priority register (SVPR0)
M, A, P, S, PRIORITY, VECTOR
0x5_0210
Serial interrupt 0 destination register (SDR0)
P0
0x5_0220
Serial interrupt 1 vector/priority register (SVPR1)
M, A, P, S, PRIORITY, VECTOR
0x5_0230
Serial interrupt 1 destination register (SDR1)
P0
0x5_0240
Serial interrupt 2 vector/priority register (SVPR2)
M, A, P, S, PRIORITY, VECTOR
0x5_0250
Serial interrupt 2 destination register (SDR2)
P0
0x5_0260
Serial interrupt 3 vector/priority register (SVPR3)
M, A, P, S, PRIORITY, VECTOR
Chapter 11. Embedded Programmable Interrupt Controller (EPIC) Unit
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