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Sequential Circuits
Example 6-16 Sequential Process Without a Sensitivity List
process ...
begin
wait until <CLK'EVENT | not CLK’ STABLE> and CLK = <'0' | '1'>;
... -- a synchronous part may be specified here.
end process;
Note: XST does not support clock and clock enable descriptions within the same Wait statement.
Instead, code these descriptions as in Example 6-17.
Note: XST does not support Wait statements for latch descriptions.
Example 6-17 Clock and Clock Enable
Not supported:
wait until CLOCK'event and CLOCK = '0' and ENABLE = '1' ;
Supported:
wait until CLOCK'event and CLOCK = '0' ;
if ENABLE = '1' then ...
Examples of Register and Counter Descriptions
Example 6-18 describes an 8-bit register using a process with a sensitivity list. Example
6-19 describes the same example using a process without a sensitivity list containing a Wait
statement.
Example 6-18 8 bit Register Description Using a Process with a Sensitivity List
entity EXAMPLE is
port (
DI : in BIT_VECTOR (7 downto 0);
CLK : in BIT;
DO : out BIT_VECTOR (7 downto 0) );
end EXAMPLE;
architecture ARCHI of EXAMPLE is
begin
process (CLK)
begin
if CLK'EVENT and CLK = '1' then
DO <= DI ;
end if;
end process;
end ARCHI;
Example 6-19 8 bit Register Description Using a Process without a Sensitivity List
entity EXAMPLE is
port (
DI : in BIT_VECTOR (7 downto 0);
CLK : in BIT;
DO : out BIT_VECTOR (7 downto 0) );
end EXAMPLE;
XST User Guide
8.1i
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