Download Xilinx XST User Guide

R
Chapter 2: HDL Coding Techniques
Specify initial contents for a single-port RAM using the following Verilog code.
These coding examples are accurate as of the date of publication. You can download any
updates to these examples from
ftp://ftp.xilinx.com/pub/documentation/misc/examples_v7.zip.
//
// Initializing Block RAM (Single-Port BRAM)
//
module v_rams_20a (clk, we, addr, di, do);
input clk;
input we;
input [5:0] addr;
input [19:0] di;
output [19:0] do;
reg [19:0] ram [63:0];
reg [19:0] do;
initial begin
ram[63] =
ram[60] =
ram[57] =
ram[54] =
ram[51] =
ram[48] =
ram[45] =
ram[42] =
ram[39] =
ram[36] =
ram[33] =
ram[30]
ram[27]
ram[24]
ram[21]
ram[18]
ram[15]
ram[12]
ram[9]
ram[6]
ram[3]
ram[0]
=
=
=
=
=
=
=
=
=
=
=
20'h0200A;
20'h04000;
20'h00300;
20'h0203B;
20'h08201;
20'h02500;
20'h04002;
20'h00500;
20'h04003;
20'h00102;
20'h00301;
ram[62]
ram[59]
ram[56]
ram[53]
ram[50]
ram[47]
ram[44]
ram[41]
ram[38]
ram[35]
ram[32]
=
=
=
=
=
=
=
=
=
=
=
20'h00300;
20'h08601;
20'h08602;
20'h08300;
20'h00500;
20'h00340;
20'h08300;
20'h08101;
20'h0241E;
20'h02122;
20'h00102;
ram[61]
ram[58]
ram[55]
ram[52]
ram[49]
ram[46]
ram[43]
ram[40]
ram[37]
ram[34]
ram[31]
=
=
=
=
=
=
=
=
=
=
=
20'h08101;
20'h0233A;
20'h02310;
20'h04002;
20'h04001;
20'h00241;
20'h08201;
20'h00602;
20'h00301;
20'h02021;
20'h02222;
20'h04001;
20'h00900;
20'h04002;
20'h02023;
20'h00301;
20'h00102;
20'h00301;
20'h04004;
20'h02500;
20'h0030D;
20'h0400D;
ram[29]
ram[26]
ram[23]
ram[20]
ram[17]
ram[14]
ram[11]
ram[8]
ram[5]
ram[2]
=
=
=
=
=
=
=
=
=
=
20'h00342;
20'h00302;
20'h00900;
20'h00303;
20'h04004;
20'h02137;
20'h00102;
20'h00304;
20'h02500;
20'h02341;
ram[28]
ram[25]
ram[22]
ram[19]
ram[16]
ram[13]
ram[10]
ram[7]
ram[4]
ram[1]
=
=
=
=
=
=
=
=
=
=
20'h0232B;
20'h00102;
20'h08201;
20'h02433;
20'h00301;
20'h02036;
20'h02237;
20'h04040;
20'h02500;
20'h08201;
end
always @(posedge clk)
begin
if (we)
ram[addr] <= di;
do <= ram[addr];
end
endmodule
232
www.xilinx.com
XST User Guide
8.1i