Download USB930HxADBD Adapter Board User's Manual

USB930HxADBD
Adapter Board
User’s Manual
April 1997
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Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
*Third-party brands and names are the property of their respective owners.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
Copyright © INTEL CORPORATION, 1996, 1997
CONTENTS
CONTENTS
1.0
INTRODUCTION .............................................................................................................. 1
2.0
INSTALLATION ................................................................................................................ 1
2.1
Installing the Adapter Board .........................................................................................1
2.2
Installing the new EPROM ........................................................................................... 4
3.0
BOARD LAYOUT.............................................................................................................. 5
4.0
FEATURES....................................................................................................................... 5
4.1
CPU Foot Print ............................................................................................................. 5
4.2
External Clock Oscillator/Crystal .................................................................................. 5
4.3
Test Points ................................................................................................................... 6
4.4
Jumpers ....................................................................................................................... 6
4.5
Evaluation Board Interface ........................................................................................... 6
4.6
Serial Communications ................................................................................................ 6
4.6.1
Using the External Serial Port ................................................................................. 7
4.6.2
Using the Internal Serial Port .................................................................................. 7
5.0
8X930XX ADAPTER BOARD SCHEMATICS .................................................................. 7
FIGURES
8X930 MICROCONTROLLER LOCATION ................................................................................... 2
ADAPTER BOARD ORIENTATION .............................................................................................. 3
EPROM ORIENTATION ............................................................................................................... 4
ADAPTER BOARD LAYOUT ........................................................................................................ 5
i
1.0
INTRODUCTION
This manual describes how to connect the USB930HxADBD daughter card to the 8x930 Family
USB Evaluation Board Rev B. The 8x930Hx chip supports one upstream USB port and four
downstream USB ports.
NOTE
Due to pin incompatibilities, this daughter card can be used with the four-port
8x930 Family USB Evaluation Board Rev B only.
2.0
2.1
INSTALLATION
Installing the Adapter Board
1.
Remove the 8x930Ax device installed on the 8x930 Family USB Evaluation Board Rev B
from the U3 socket prior to installing the adapter board. Refer to Figure 1 for the location
of socket U3
2.
Place the adapter on the evaluation board, ensuring that the connectors are properly
aligned, and press the adapter onto the evaluation board until the connectors are fully
engaged. Refer to Figure 2 for the correct orientation for the adapter board.
1
USB930HXADBD ADAPTER BOARD USER’S GUIDE
I/O Expansion
P5
12
SOF
JW20
JW14
P12V
JW3
JW8
P5V
JW15
RP1
RP2
Non-Page
Page
JW21
U11
RP5
U6
U13
Socket Justify
A12
DM2
DP3
DM3
TP TP
17 18
1
39
P6
Data Freq
1.5 3 MHz
1.5 6 MHz
12 12 MHz
DM4
TP
19
PLL0
1-2
2-3
2-3
Port4
DP4
2
40
F1
U9
PLL1
2-3
2-3
1-2
Port3
TP
16
SOCKET B
U2 SRAM Only
JW16
RP4
PLL2
2-3
1-2
1-2
Port2
TP
15
A12*
JW9
REMOVE
microcontroller
in socket U3
U15
DM1
DP2
U7
U14
RP3
U8
Port1/5
DP1
TP TP
13 14
SOCKET A
U1
U5
U12
S1
50
INT0
INT1
8x930 Family EVAL BD
REV B
TP
12
GND TP2
49
JW19
INT
U3
Q1
S2
S3
+
TP4
TP3
TP5
Y1
RESET
JW10
(PLL2)
JW11
(PLL1)
JW12
(PLL0)
1
TP9
1
GND
1
GND
39
P7 JW6
2
40
GND
TP11
1
JW18
U10
VR1
JW7
JW2
P8
UPSTREAM
PORT
P10
Low
Full
TP
20
P9
TP
21
+5V
J1
GND
Serial I/O
UART
TP1
JW5
JW13
TP6
JW23
U17
J2
U4
TP7
JW22
JW4
U16
C1
JW17
TP10
U18
JW1
TP8
A5525-01
Figure 1. 8x930 Microcontroller Location
2
USB930HXADBD ADAPTER BOARD USER’S GUIDE
I/O Expansion
P5
12
SOF
JW20
JW14
P12V
JW3
JW8
P5V
JW15
RP1
RP2
Non-Page
Page
JW21
U11
RP5
U6
U13
Socket Justify
A12
DP3
DM3
TP TP
17 18
P6
1 1 22
Port4
P6
40
DP4
DM4
TP
19
U1
Data Freq
1.5 3 MHz
1.5 6 MHz
12 12 MHz
F1
U2
U3
Port3
TP
16
SOCKET B
U2 SRAM Only
39 40
PLL0
1-2
2-3
2-3
TP
15
A12*
39
PLL1
2-3
2-3
1-2
Port2
DM2
JW16
RP4
U9
U15
PLL2
2-3
1-2
1-2
DM1
DP2
JW9
U7
U14
RP3
U8
Port1/5
DP1
TP TP
13 14
SOCKET A
U1
U5
U12
S1
50
INT0
INT1
8x930 Family EVAL BD
REV B
TP
12
GND
TP2
49
JW19
INT
Q1
S2
S3
JW1
TP8
+
C1
TP5
Y1
RESET
TP3
Y1
U16
JW4
PLL2
JW17PLL1 PLL0
2-3 2-3 1-2
1-2 2-3 2-3
1-2 1-2 2-3
TP10
TP4
1
JW10
(PLL2)
JW11
U4
Data Freq
1.5
3
1.5
6
12 12
TP9
10µ
16v
(PLL1)
JW12
TP7
2 JW6
1P7
2
3940
40
JW18
U10
VR1
JW7
JW2
P8
UPSTREAM
PORT
P10
Low
Full
TP
20
P9
TP
21
+5V
J1
GND
Serial I/O
UART
TP1
JW5
JW13
TP6
JW23
U17
J2
1
GND
P7
1
GND
39
1
GND
TP11
JW22
U18
(PLL0)
A5527-01
Figure 2. Adapter Board Orientation
3
USB930HXADBD ADAPTER BOARD USER’S GUIDE
2.2
Installing the new EPROM
If an EPROM is included in the upgrade package, you must use it to replace the EPROM that is
installed in Socket A of the evaluation board. This upgraded EPROM has the same pinout as the
original, however, it contains new RISM (Reduced Instruction Set Monitor) code. No jumper
changes are required.
NOTE
Socket A can accept either a 32K, 64K, or 128K EPROM. Because of this,
when you install the 32K EPROM provided by Intel there will be four holes
left open by the notch. See Figure 3 for the correct orientation of the EPROM.
I/O Expansion
JW20
RP1
RP2
P12V
JW3
JW8
P5V
JW15
Leave 4 holes
by notch OPEN
Port1/5
DP1
DM1
U6
U13
TP TP
13 14
SOCKET A
U1
U5
U12
Socket Justify
TP2
JW14
Non-Page
Page
JW21
U11
RP5
Port2
DP2
A12
DM2
TP
16
J
SOCKE
U2 SRA
TP
15
A12*
JW9
U7
U14
RP3
S1
INT0
50
INT1
GND
P5
12
SOF
8x930 Family EVAL BD
REV B
TP
12
49
JW19
INT
Port3
A5528-01
Figure 3. EPROM Orientation
4
USB930HXADBD ADAPTER BOARD USER’S GUIDE
3.0
BOARD LAYOUT
Figure 4 shows the layout of the board and the major components.
1 2
10µ
16v
1 2
U2
3"
P6
P7
Y1
U1
39 40
39 40
PLL2
2-3
1-2
1-2
PLL1 PLL0
2-3 1-2
2-3 2-3
1-2 2-3
Data Freq
1.5
3
1.5
6
12 12
3"
Top View
Side View
Interfaces to 82930
USBM Eval Board
A5526-01
Figure 4. Adapter Board Layout
4.0
4.1
FEATURES
CPU Foot Print
The Adapter Board has the foot print for a 68-pin PLCC socket to match the pinout of the
8x930Hx.
4.2
External Clock Oscillator/Crystal
The board provides space for a crystal and a capacitor to use the internal oscillator of the 8x930Hx
and also contains a clock oscillator that produces an independent external clock source for the
8x930Hx. Only one clock source can be used at a time. By default the clock oscillator is used and
the crystal and capacitor are not populated. To use the internal oscillator, you must cut Jumper
JW1 and install the appropriate crystal and capacitor.
5
USB930HXADBD ADAPTER BOARD USER’S GUIDE
4.3
Test Points
The board contains test points for CLK12MHZ, XTAL2, and AVCC.
4.4
Jumpers
The board contains jumpers to allow the 8x930Hx device to be reconfigured. Three 3-pin jumpers
are used to select the core operating frequency and the USB data rate. Figure 1 illustrates jumper
configurations:
Table 1. Jumper Configuration
PLL2 JW4
PLL1 JW3
PLL0 JW2
USB Data
Rate
Core
Frequency
XTAL1
2-3
2-3
1-2
1.5 Mbps
3 MHz
6 MHz
1-2
2-3
2-3
1.5 Mbps
6 MHz
12 MHz
1-2
1-2
2-3
12 Mbps
12 MHz
12 MHz
JW1 allows the clock oscillator to be disconnected from the 8x930Hx so that a crystal can be
used. To install your own crystal, you must either cut JW1 or remove the existing clock oscillator.
NOTE
When selecting 1.5Mbps with a 3MHz core, a 6MHz crystal must be installed
on the board.
4.5
Evaluation Board Interface
The 8x930Hx Adapter Board interfaces to the 8x930 Family Evaluation. Board. Rev B through
two 40-pin female headers. The headers are surface mounted on the solder side of the board. The
interface is “duplicated” physically and electrically on the component side of the board to allow
probing access.
4.6
Serial Communications
The adapter board contains the new 8x930Hx USB chip. This device has a default start-up internal frequency of 3 MHz. You can change this frequency to 12 MHz by clearing the LC bit located
in the PCON register. You can switch back to 3 MHz by setting the LC bit. Readers are encouraged to consult the 8x930Ax, 8x930Hx Universal Serial Bus Microcontroller User’s Manual
(order number 272949) for more information on this subject.
6
USB930HXADBD ADAPTER BOARD USER’S GUIDE
The flexibility of frequency changes for power saving has a direct impact on baud rate and serial
communication. To allow debugging sessions without risk of board-PC communication loss, a
number of changes have been added to the RISM code. To establish communication between the
evaluation board and the debugger (Keil, PLC, or Tasking software) use either the external serial
link (recommended) or the internal serial link.
4.6.1
Using the External Serial Port
You are encouraged strongly to use the external serial port to communicate with the debugger
environment. When this serial port is used, the baud rate is 19200 (make sure you set the debugger
software to use the same rate) and all internal timers are available. The internal serial port is then
free and can be used by your application. One interrupt (intr0), however, is used by the UART
and cannot be used. The priority should not be changed.
The external serial port is labeled “UART” on the board To enable this port, set the UARTC
switch to the “ON” position.
When using this port, you can set or clear the LC bit using the SETB and CLR instructions. There
are no restrictions to your code.
4.6.2
Using the Internal Serial Port
The use of the internal serial port to communicate with the debugger is not recommended. When
you use this serial port, the baud rate is fixed at 9600 (you must set the debugger software to use
the same rate) and timer-two is used by the RISM to generate the baud rate, making this timer
unavailable for your application. The internal serial port is no longer available since it used to
communicate with the debugger. Do not change the interrupt priority. The external interrupts,
intr0 and intr1, are both available.
When using this port, you can still set or clear the LC bit. However, you cannot use the SETB and
CLR instructions to do. So you must use an extended call to a routine inside the RISM that sets
or clears the bit. Instead of using “SETB LC” you must use “ECALL 0FF0083” and instead of
using “CLR LC” use “ECALL 0FF008B”.
5.0
8X930XX ADAPTER BOARD SCHEMATICS
The pages that follow provide you with schematics for the adapter board. These files are also
available on the Intel World-Wide Web sit at www.intel.com.
7
USB930HXADBD ADAPTER BOARD USER’S GUIDE
8
A
B
C
D
P2.[0:7]
P1.[0:7]
P3.[0:7]
P0.[0:7]
P0.7
P0.5
P0.3
P0.1
P0.7
P0.5
P0.3
P0.1
1
Although Intel has verified this design to be functional,
Intel assumes no responsibility for any errors which may
appear in the design. Intel reserves the right to modify
this design without notice.
1
P3.0
P3.2
P3.4
P3.6
P3.0
P3.2
P3.4
P3.6
P1.0
P1.2
P1.4
P1.6
P1.0
P1.2
P1.4
P1.6
P2.3
P2.1
P2.7
P2.5
P2.3
P2.1
P2.7
P2.5
2
2
P5V
P5V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J6
P6
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
P2.6
P2.4
P2.2
P2.0
P2.6
P2.4
P2.2
P2.0
P0.6
P0.4
P0.2
P0.0
P0.6
P0.4
P0.2
P0.0
3
P3.1
P3.3
P3.5
P3.7
P3.1
P3.3
P3.5
P3.7
3
P1.1
P1.3
P1.5
P1.7
P1.1
P1.3
P1.5
P1.7
AVCC
SOF*
EA*
ALE
PSEN*
AVCC
SOF*
EA*
ALE
PSEN*
P5V
P5V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
File
4
4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
HELSCON.SCH
J7
P7
RESET
OVRI*
DP3
DM3
UPWEN*
DP1
DM1
DP4
DM4
DP2
DM2
DP0
DM0
P5V
P5V
AVCC
SOF*
PSEN*
EA*
ALE
DP0
DM0
RESET
OVRI*
DP3
DM3
UPWEN*
DP1
DM1
DP4
DM4
DP2
DM2
Drawn by
B
Size
RESET
OVRI*
DP3
DM3
UPWEN*
DP1
DM1
DP4
DM4
DP2
DM2
DP0
DM0
AVCC
SOF*
PSEN*
EA*
ALE
6
CMJ
5
FCSM No.
Date
2-Apr-1997
0001
11:13:13
DWG No.
Sheet
2
of
6
2
USB930HxADBD Adapter Bd.
Intel Corporation
CEG System Engineering Boards and ASICs
5000 W. Chandler Blvd.
Chandler, AZ 85226
5
A
Rev
A
B
C
D
A
B
C
4
1
1
OUT
VCC
Clock Osc.
12.000 MHz
GND
U1
C8
10 uF
NC
P5V
Although Intel has verified this design to be functional,
Intel assumes no responsibility for any errors which may
appear in the design. Intel reserves the right to modify
this design without notice.
P1.[0:7]
P3.[0:7]
P0.[0:7]
P2.[0:7]
5
8
CLK12MHZ
P5V
2
TP1
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
P5V
1
1
JW1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
2
AD7/P0.7
AD6/P0.6
AD5/P0.5
AD4/P0.4
AD3/P0.3
AD2/P0.2
AD1/P0.1
AD0/P0.0
Vssp
Vccp
P3.0/RXD
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
P3.5/T1
P3.6/WR#
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
3
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
HELSINKI
U2
A8/P2.0
A9/P2.1
A10/P2.2
A11/P2.3
A12/P2.4
A13/P2.5
A14/P2.6
A15/P2.7
Vss
Vcc
EA#
ALE
PSEN#
Reserved
Reserved
UPWEN#
OVRI#
A16/P3.7/RD#
P1.0/T2
P1.1/T2EX
P1.2/ECI
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3/WAIT#
A17/P1.7/CEX4/WCLK
Vcc
Vss
XTAL1
XTAL2
AVcc
RESET
PLLSEL1
PLLSEL2
Y1
12.000 MHz
C1
30 pF
XTAL1
3
C2
30 pF
XTAL2
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
P3.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
TP2
AVCC
DP5
DM5
DP1
DM1
Reserved
DP0
DM0
ECAP
Vssp
Vccp
SOF#
DP3
DM3
Reserved
DP2
DM2
PLLSEL0
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
TP3
PLLSEL1
PLLSEL2
ECAP
C3
File
0.1 uF
2
JW2
4
2
C6
0.1 uF
4
PLLSEL0
C5
0.1 uF
1 uF
C7
P5V
C4
0.1 uF
1
3
2
1
UPWEN*
OVRI*
EA*
ALE
PSEN*
HELSSOC.SCH
JW3
C9
0.1 uF
1
3
D
1
1
2
1
3
JW4
2-3
1-2
1-2
1-2
AVCC
RESET
2-3
2-3
1-2
12 Mbps
1.5 Mbps
1.5 Mbps
Drawn by
B
Size
12 MHz
6 MHz
3 MHz
12 MHz
12 MHz
6 MHz
XTAL1
AVCC
RESET
DP2
DM2
SOF*
DP3
DM3
DP0
DM0
DP4
DM4
DP1
DM1
UPWEN*
OVRI*
EA*
ALE
PSEN*
6
CMJ
5
FCSM No.
Date
2-Apr-1997
0001
11:13:33
DWG No.
Sheet
1
of
6
2
USB930HxADBD Adapter Bd.
Intel Corporation
CEG System Engineering Boards and ASICs
5000 W. Chandler Blvd.
Chandler, AZ 85226
2-3
2-3
PLLSEL2 PLLSEL1 PLLSEL0 USB data rate Core frequency
DP2
DM2
SOF*
DP3
DM3
DP0
DM0
DP4
DM4
DP1
DM1
5
A
Rev
A
B
C
D