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Signal Spy
signal_release
signal_release
This reference section describes the following:
•
VHDL Procedure — signal_release()
•
Verilog Task — $signal_release()
•
SystemC Function— signal_release()
The signal_release() call releases any force that was applied to an existing VHDL signal,
Verilog register/net, or SystemC signal (called the dest_object). This allows you to release
signals, registers or nets at any level of the design hierarchy from within a VHDL architecture
or Verilog or SystemC module (e.g., a testbench).
A signal_release works the same as the noforce command. Signal_release can be called
concurrently or sequentially in a process.
By default this command uses a backslash (\) as a path separator. You can change this behavior
with the SignalSpyPathSeparator variablie in the modelsim.ini file.
VHDL Syntax
signal_release(<dest_object>, <verbose>)
Verilog Syntax
$signal_release(<dest_object>, <verbose>)
SystemC Syntax
signal_release(<dest_object>, <verbose>)
Returns
Nothing
Arguments
•
dest_object
Required string. A full hierarchical path (or relative downward path with reference to the
calling block) to an existing VHDL signal, Verilog register/net, or SystemC signal. Use the
path separator to which your simulation is set (i.e., "/" or "."). A full hierarchical path must
begin with a "/" or ".". The path must be contained within double quotes.
•
verbose
Optional integer. Possible values are 0 or 1. Specifies whether you want a message reported
in the Transcript stating that the signal is being released and the time of the release.
0 — Does not report a message. Default.
1 — Reports a message.
ModelSim User’s Manual, v6.3g
May 2008
311