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I2S Controller 21.8.4 I2S Global Status Registers I2S Global Status Registers 21 I2SGlSts 31 30 RSVD 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rx2_fif o_half_ full rx2_fifo _empty rx2_fifo_f ull tx2_fifo_h alf_ empty tx2_fifo_e mpty tx2_fifo_ full rx1_fifo _half_ full rx1_fifo _empty rx1_fifo _full tx1_fifo_ half_ empty tx1_fifo_ empty tx1_fifo_f ull rx0_fifo_h alf_ full rx0_fifo_e mpty 8 7 6 5 4 3 2 1 0 Rx0_ overflow Tx2_ underflow Tx1_ underflow Tx0_ underflow 15 14 13 12 11 10 9 rx0_fifo _full tx0_fifo _half_ empty tx0_fifo _empty tx0_fifo _full Rx2_ underflow Rx1_ underflow Rx0_ underflow Tx2_ Tx1_ Tx0_ Rx2_ Rx1_ overflow overflow overflow overflow overflow Address: 0x8082_0008 - Read/Write Default: 0x0001_2492 Definition: UART Data Register Bit Descriptions: 672 RSVD: Reserved. Unknown During Read. Tx0_underflow: when = 1, TX0 FIFO has underflowed. Tx1_underflow: when = 1, TX0 FIFO has underflowed. Tx2_underflow: when = 1, TX0 FIFO has underflowed. Rx0_overflow: when = 1, RX0 FIFO has overflowed and the FIFO pointer is currently pointing at the last data received before the overflow occurred. Rx1_overflow: when = 1, RX1 FIFO has overflowed and the FIFO pointer is currently pointing at the last data received before the overflow occurred. Rx2_overflow: when = 1, RX2 FIFO has overflowed and the FIFO pointer is currently pointing at the last data received before the overflow occurred. Tx0_overflow: when = 1, the tx0 FIFO is full and an attempt has been made to write data to it by the APB or DMA. This bit is cleared by writing a 0 to it. EP9307 User’s Manual - DS667UM1 Copyright 2004 Cirrus Logic
