Download ModelSim User's Manual - Electronics and Computer Science

Verilog and SystemVerilog Simulation
Compiling Verilog Files
Note
Compilation order may matter when using SystemVerilog packages. As stated in the
IEEE std p1800-2005 LRM, section entitled Referencing data in packages, which states:
"Packages must exist in order for the items they define to be recognized by the scopes in
which they are imported.”
Incremental compilation is made possible by deferring these bindings, and as a result some
errors cannot be detected during compilation. Commonly, these errors include: modules that
were referenced but not compiled, incorrect port connections, and incorrect hierarchical
references.
Example 6-2. Incremental Compilation Example
Contents of testbench.sv
module testbench;
timeunit 1ns;
timeprecision 10ps;
bit d=1, clk = 0;
wire q;
initial
for (int cycles=0; cycles < 100; cycles++)
#100 clk = !clk;
design dut(q, d, clk);
endmodule
Contents of design.v:
module design(output bit q, input bit d, clk);
timeunit 1ns;
timeprecision 10ps;
always @(posedge clk)
q = d;
endmodule
Compile the design incrementally as follows:
ModelSim> vlog testbench.sv
.
# Top level modules:
# testbench
ModelSim> vlog -sv test1.v
.
# Top level modules:
# dut
Note that the compiler lists each module as a top-level module, although, ultimately, only
testbench is a top-level module. If a module is not referenced by another module compiled in
the same invocation of the compiler, then it is listed as a top-level module. This is just an
informative message and can be ignored during incremental compilation.
142
ModelSim User’s Manual, v6.2g
February 2007