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Download Arria 10 Transceiver PHY User Guide
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1-2 UG-A10XCVR 2013.12.02 Device Transceiver Layout Table 1-2: Data Rates Supported by GT Transceiver Channel Type (4) Data Rates Device Variant (3) GT Chip-to-Chip Backplane 611 Mbps to 28.1 Gbps 611 Mbps to 17.4 Gbps Note: The device data rates are dependent on the device speed grade. Refer to Arria 10 Device Datasheet for details on available speed grades and supported data rates. Related Information Arria 10 Device Datasheet Device Transceiver Layout Figure 1-1: Arria 10 FPGA Architecture Block Diagram Transceiver Channels PCI Express Gen3 Hard IP PLLs Hard IP Per Transceiver: Standard PCS, PCIe Gen 3 PCS, Enhanced PCS PCI Express Gen3 Hard IP Variable Precision DSP Blocks M20K M20K Internal Internal Memory Memory Blocks Blocks I/O PLLs Hard Memory Controllers, General-Purpose I/O Cells, LVDS Core Logic Fabric Variable Precision DSP Blocks M20K M20K Internal Internal Memory Memory Blocks Blocks Core Logic Fabric I/O PLLs Hard Memory Controllers, General-Purpose I/O Cells, LVDS Variable Precision DSP Blocks M20K M20K Internal Internal Memory Memory Blocks Blocks Transceiver Channels (4) Hard IP Per Transceiver: Standard PCS, PCIe Gen 3 PCS, Enhanced PCS PLLs PCI Express Gen3 Hard IP PCI Express Gen3 Hard IP The transceiver channels are placed on the left side periphery in most Arria 10 devices. For larger Arria 10 devices, additional transceiver channels are placed on the right side periphery. Because the GT transceiver channels are designed for peak performance, they do not have a reduced power mode of operation. Altera Corporation Arria 10 Transceiver PHY Overview Send Feedback
