Download 10-Gbps Ethernet MAC MegaCore Function User Guide

9–12
Chapter 9: Interface Signals
Table 9–6. MII Signals
Signal
Direction
Input
tx_clkena
Input
tx_clkena_half_rate
Width
Description
1
The TX clock enable provided by the PHY IP to the
MAC. This clock divides gmii_tx_clk_clk down to
25 MHz for 100 Mbps mode and 2.5 MHz for
10 Mbps mode.
1
The TX half-clock enable provided by the PHY IP to
the MAC. This clock divides gmii_tx_clk_clk down
to 12.5 MHz for 100 Mbps mode and 1.25 MHz for
10 Mbps mode.
9.0.6. Unidirectional Signals
Table 9–8 describes the unidirectional signals. These signals are present only when
you turn on the Enable unidirectional mode option.
Table 9–7. Unidirectional Signals
Signal
Direction
Width
Description
unidirectional_en
Output
1
When asserted, this signal indicates the state of tx_
unidir_control register bit 0.
unidirectional_remote_fault_dis
Output
1
When asserted, this signal indicates the state of tx_
unidir_control register bit 1.
9.0.7. Avalon-MM Programming Interface Signals
Table 9–8 describes the Avalon-MM programming interface signals.
Table 9–8. Avalon-MM CSR Interface Signals
Signal
Direction
Width
Description
csr_address[]
Input
13
Use this bus to specify the register address you want to
read from or write to.
csr_read
Input
1
Assert this signal to request a read.
Output
32
Carries the data read from the specified register.
csr_write
Input
1
Assert this signal to request a write.
csr_writedata[]
Input
32
Carries the data to be written to the specified register.
csr_readdata[]
When asserted, this signal indicates that the IP core is
busy and not ready to accept any read or write
requests.
csr_waitrequest
10-Gbps Ethernet MAC MegaCore Function User Guide
Output
1
■
During read operations, the csr_readdata[] is not
valid until csr_waitrequest is deasserted.
■
During write operations, the data in
csr_writedata[] is not written until
csr_waitrequest is deasserted.
August 2014 Altera Corporation