Download 10-Gbps Ethernet MAC MegaCore Function User Guide

Additional Information
This chapter provides additional information about the document and Altera.
Document Revision History
The following table shows the revision history for this document.
Date
Version
August 2014
February 2014
May 2013
August 2014
3.4
3.3
3.2.1
Altera Corporation
Changes
■
Modified Chapter 2, Getting Started with Altera IP Cores to describe the new Quartus II
software IP design flow. The IP core is upgraded to support the new IP Catalog.
■
Updated the parameter names in Table 2–1 on page 2–8.
■
Added a new feature—Unidirectional mode.
■
Added a new parameter—Enable unidirectional mode.
■
Added TX Unidirectional registers and signals.
■
Added 36-bit format to the fault signals in “Error Handling (Link Fault)” on page 7–21
■
Removed information about Arria GX, HardCopy IV GX, and Stratix II GX devices. Altera
no longer supports these devices.
■
Removed chapters about 1G/10GbE MAC and 10M-10GbE MAC with IEEE 1588v2 design
examples.
■
Updated Table 1–2 on page 1–3 with 1G/10Gbps Ethernet PHY support.
■
Edited information for the avalon_st_rxstatus_error register. The error status is no
longer invalid when CRC and/or padding removal is enabled.
■
Added clock information in “Pause Frame Transmission” on page 7–18.
■
Added Cyclone V performance and resource utilization data for 10GbE MAC in Table 1–5
on page 1–5 and Table 3–8 on page 3–19.
■
Edited the FWD_PFC reset value in Table 8–4 on page 8–17.
■
Edited the PMA analog and digital delay information in Table 8–6 and Table 8–7 on
page 8–19.
■
Renamed tx_ingress_timestamp_valid to
tx_etstamp_ins_ctrl_residence_time_update.
10-Gbps Ethernet MAC MegaCore Function User Guide