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Chapter 2: HDL Coding Techniques
Verilog Code
Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock, an
asynchronous parallel load, a serial in, and a serial out.
module shift (C, ALOAD, SI, D, SO);
input C, SI, ALOAD;
input [7:0] D;
output SO;
reg [7:0] tmp;
always @(posedge C or posedge ALOAD)
begin
if (ALOAD)
tmp = D;
else
begin
tmp = {tmp[6:0], SI};
end
end
assign SO = tmp[7];
endmodule
8-bit Shift-Left Register with Positive-Edge Clock, Synchronous Parallel
Load, Serial In, and Serial Out
Note: For this example, XST does not infer SRL16.
The following table shows pin definitions for an 8-bit shift-left register with a positiveedge clock, a synchronous parallel load, a serial in and a serial out.
IO Pins
Description
C
Positive-Edge Clock
SI
Serial In
SLOAD
Synchronous Parallel Load (active High)
D[7:0]
Data Input
SO
Serial Output
VHDL Code
Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock,
synchronous parallel load, serial in, and serial out.
library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(
C, SI, SLOAD : in std_logic;
D : in std_logic_vector(7 downto 0);
SO : out std_logic
);
end shift;
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