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Multiplexers
4-to-1 MUX Using Tristate Buffers
The following table shows pin definitions for a 4-to-1 1-bit MUX using tristate buffers.
IO Pins
Description
a, b, c, d
Data Inputs
s[3:0]
MUX Selector
o
Data Output
VHDL Code
Following is the VHDL code for a 4-to-1 1-bit MUX using tristate buffers.
library ieee;
use ieee.std_logic_1164.all;
entity mux is
port (
a, b, c, d : in std_logic;
s : in std_logic_vector (3 downto 0);
o : out std_logic
);
end mux;
architecture archi of mux is
begin
o <= a when (s(0)=’0’) else
o <= b when (s(1)=’0’) else
o <= c when (s(2)=’0’) else
o <= d when (s(3)=’0’) else
end archi;
’Z’;
’Z’;
’Z’;
’Z’;
Verilog Code
Following is the Verilog Code for a 4-to-1 1-bit MUX using tristate buffers.
module mux (a, b, c, d, s, o);
input a, b, c, d;
input [3:0] s;
output o;
assign o
assign o
assign o
assign o
endmodule
=
=
=
=
s[3]
s[2]
s[1]
s[0]
?
?
?
?
a
b
c
d
:1’bz;
:1’bz;
:1’bz;
:1’bz;
No 4-to-1 MUX
The following example does not generate a 4-to-1 1-bit MUX, but a 3-to-1 MUX with 1-bit
latch. The reason is that not all selector values were described in the If statement. It is
supposed that for the s=11 case, "O" keeps its old value, and therefore a memory element is
needed.
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