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Download Altera Stratix GX User guide
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GigE Mode Clocking Figure 6–22. Receiver PLL CRU Clock From Transmitter PLL is Disabled by Adding RX_CRUCLK If the TX_CORECLK is enabled, the training receiver CRU clock from transmitter PLL is not enabled, and other default options are also enabled, this configuration has an independent rx_cruclk port that feeds the receiver PLL reference clock. This input clock port is available only when the receiver PLL is not trained by the transmitter PLL. 6–22 Stratix GX Transceiver User Guide Altera Corporation January 2005
