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Download Fall2011 Workshop Handout
Transcript
8/29/2011 Fitter Settings – Fitter Effort Standard Fit – Highest effort – Longest compile time Fast Fit – Faster compile – Possibly lesser performance Auto Fit – Compile stops after meeting timing – Conserves CPU time – Will mimic standard fit for hardto-fit designs – Default for new designs One fitting attempt 71 Tcl: set_global_assignment –name FITTER_EFFORT “<Effort Level>” I/O Planning Need • I/O standards increasing in complexity • FPGA/CPLD I/O structure increasing in complexity – Results in increased pin placement guidelines • PCB development performed simultaneously with FPGA design • Pin assignments need to be verified earlier in design cycle • Designers need easy way to transfer pin assignments into board tools 72 36
