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Errata Sheet Functional Deviations between individual trap types does not fully comply with the architectural definition. The current TriCore1 CPU implements the following priority order between an asynchronous trap, a synchronous trap, and an interrupt: 1. 2. 3. 4. Synchronous traps detected in Execute pipeline stage (highest priority). Asynchronous trap. Interrupt. Synchronous trap detected in Decode pipeline stage (lowest priority). Within these groups the following priorities are implemented: Table 8 Synchronous Trap Priorities (Detected in Execute Stage) Priority Type of Trap 1 VAF-D 2 VAP-D 3 MPR 4 MPW 5 MPP 6 MPN 7 ALN 8 MEM 9 DSE 10 OVF 11 SOVF 12 Breakpoint Trap (BAM) Table 9 Asynchronous Trap Priorities Priority Type of Trap 1 NMI 2 DAE TC1766, ES-BD, BD 57/182 Rel. 1.3, 2014-02-21
