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Errata Sheet
Functional Deviations
Under most circumstances this problem is not detectable, since the SRAM
memories used hold the previous values read with the data merged from the
store operation. However, if another bus master accesses the Data Scratchpad
RAM within this sequence, but before the LD.D is re-issued, the SRAM memory
outputs no longer default to the required data and the data returned by the LD.D
instruction is incorrect.
Example 1:
a12 = 0xd0001020
a13 = 0x00180012
...
ST.Q [a12/a13+c]0, d14
LD.D e10, [a12/a13+c]2
...
Example 2:
a12 = 0xd0001020
a13 = 0x00180012
...
ST.Q [a12/a13+c]0, d14
LD.W d2, [a4]; Previous ST.Q -> Store Buf
LD.D e10, [a12/a13+c]2 ; ST.Q still in Store Buf
...
Workaround
Wherever possible, double-word load instructions using circular addressing
mode should be constrained such that their effective address (Base+Index) is
word aligned.
Where this is not possible, and where it cannot be guaranteed that the CPU
store buffer will not contain an outstanding store operation which could conflict
with the LD.D instruction as described previously, the LD.D instruction must be
preceded by a NOP.
...
ST.Q [a12/a13+c]0, d14
NOP
LD.D e10, [a12/a13+c]2
TC1766, ES-BD, BD
84/182
Rel. 1.3, 2014-02-21