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Download GRLIB IP Core User`s Manual
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AEROFLEX GAISLER 23.3 167 GRIP Configuration options Table 170 shows the configuration options of the core (VHDL generics). Table 170.Configuration options Generic name Function Allowed range Default tech Target technology 0 - NTECH inferred clk_mul Clock multiplier, used in clock scaling. Not all techbologies support clock scaling. 1 clk_div Clock divisor, used in clock scaling. Not all technologies support clock scaling. 1 sdramen When this generic is set to 1 the core will generate a clock on the SDCLK. Not supported by all technologies. See technology specific description. 0 noclkfb When this generic is set to 0 the core will use the CGI.PLLREF input as feedback clock for some technologies. See technology specific description. 1 pcien When this generic is set to 1 the PCI clock is activated. Otherwise the PCICLKIN input is typically unused. See technology specific descriptions. 0 pcidll When this generic is set to 1, a DLL will be instantiated for the PCI input clock for some technologies. See the technology specific descriptions. 0 pcisysclk When this generic is set to 1 the clock generator will use the pciclkin input as the main clock reference. This also requires generic pcien to be set to 1. 0 freq Clock frequency in kHz 25000 clk2xen Enables 2x clock output. Not available in all technolgies and may have additional options. See technology specific description. 0 clksel Enable clock select. Not available in all technologies. 0 clk_odiv ProASIC3 output divider. Only used in ProASIC3 technology. 0
