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2.3 POWER
The power consumption of CMOS logic circuits [58] such as processor and cache logic is
approximated by
P = ACV 2 f + Pshort + Pleak
(4).
The power consumption of CMOS logic consists of components: dynamic power
Pd = ACV 2 f which is caused by signal line switching; short circuit power Pshort which is
caused by through-type current within the cell; and leak power Pleak which is caused by
leakage current. Here f is the operating frequency, A is the activity of the gates in the
system, C is the total capacitance seen by the gate outputs, and V is the supply voltage. Of
these three components, dynamic power dominates and accounts for 70% or more, Pshort
accounts for 10-30%, and Pleak accounts for about 1% [51]. Therefore, CMOS circuit
power consumption is approximately proportional to the operating frequency and the
square of supply voltage when ignoring the effects of short circuit power and leak power.
2.4 POWER-AWARE COMPUTING
Power-aware computing describes the use of power-aware components to save energy.
Power-aware components come with a set of power-performance modes. A high
performance mode consumes more power than a low performance mode but provides
better performance. By scheduling the power-aware components among different powerperformance modes according to the processing needs, a power-aware system can reduce
the power consumption while delivering the performance required by an application.
Power aware components, including processor, memory, disk, and network controller
were first available to battery-powered mobile and embedded systems. Similar
technologies have recently emerged in high end server products.
In this chapter, we focus on power-aware computing using power-aware processors.
Several approaches are available for CPU power control. A DVFS (dynamic voltage
frequency scaling) capable processor is equipped with several performance modes, or
operating points. Each operating point is specified by a frequency and core voltage pair.
An operating point with higher frequency provides higher peak performance but
consumes more power. Many current server processors support DVFS. For example, Intel
Xeon implements SpeedStep, and AMD Opteron supports PowerNow. SpeedStep and
PowerNow are trademarked by Intel and AMD respectively; this marketing language
labels a specific DVFS implementation.
For DVFS capable processors, scaling down voltage reduces power quadratically.
However, scaling down the supply voltage often decreases the operating frequency and
causes performance degradation. The maximum operating frequency of the CPU is
roughly linear to its core voltage V, as described by the following equation [58]:
f max ∝ (V − Vthreshold ) 2 / V
(5).
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