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Download ADSP-2137x SHARC ® Processor Hardware
Transcript
Sony/Philips Digital Interface audio streams and passing them via the SPORTs to internal memory for processing-or using the transmitter to encode audio or digital data and transfer it to another S/PDIF receiver in the audio system. is important to be familiar with serial digital audio interface Itstandards IEC-60958, EIAJ CP-340, AES3 and AES11. Pin Descriptions Table 10-2 provides descriptions of the pins used for the S/PDIF transmitter. Table 10-2. S/PDIF Transmitter Pin Descriptions Internal Node I/O Description DIT_CLK_I Input Serial clock. Controls the rate at which serial data enters the S/PDIF module. This is typically 64 time slots.1 DIT_DAT_I Input Serial Data. The format of the serial data can be I2S, and right- or left-justified. DIT_FS_I Input Serial Frame Sync. DIT_HFCLK_I Input Input sampling clock. The over sampling clock (which is divided down according to the FREQMULT bit in the transmitter control register to generate the biphase clock) DIT_EXTSYNC_I Input External Synchronization. Used for synchronizing the internal frame counter with an external frame sync signal. External synchronisation is enabled with bit 15 (DITCTL register). ADSP-2137x SHARC Processor Hardware Reference 10-3
