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Download ADSP-2137x SHARC ® Processor Hardware
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Serial Ports channel. When the word count reaches zero, the SPORT generates an interrupt, then automatically stops the DMA channel. Shared Channels Both the A and B channels share a common interrupt vector in the interrupt-driven data transfer mode, regardless of whether they are configured as a transmitter or receiver. The SPORT generates an interrupt when the transmit buffer has a vacancy or the receive buffer has data. To determine the source of an interrupt, applications must check the transmit or receive data buffer status bits (DXS_A, DXS_B) in SPCTLx registers and for DMA the corresponding status bits in the SPMCTLx registers. However note in most cases if both channels are enabled with the same DMA count, there is no need to check the status since both channel interrupts are close to each other. Standard DMA does not function properly in I2S/left-justified mode when two channels (A and B) are enabled with different DMA count values. In this case, the interrupt is generated for the least count only. If both the A and B channels of the SPORTs are used in I2S/left-justified mode with DMA enabled, then the DMA count value should be the same for both channels. This does not apply to chained DMA. Error Detection Similar to previous SHARC processors, the SPORTs can return the status of data buffer underflow and overflow conditions. Additionally, the SPORTs can also detect frame syncs that are occurring early, even before the last transmit or receive completes. To detect these errors, the processor has an error interrupt (SPERRI vector interrupt) that is shared for all SPORTs together. It is triggered on a data underflow, data overflow, or frame sync error in their respective channels. An interrupt is triggered and programs simply read the SPERRSTAT register which reduces the processor ADSP-2137x SHARC Processor Hardware Reference 7-51
