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Download Flexible architecture for an embedded interrupt controller
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U.S. Patent Jun. 4, 2002 Sheet 1 of 8 US 6,401,154 B1 processor address bus J CPU Core @ no processor data bus ,-----------.---- m. P 1e 1 M.ED$2m.Ou3m .L B w P A 8G 66 T Wbmmmr w“m."rmmcm 16% L I-Ul.l w.“inr E Vl mm“ m _r m m w| n.-.. 1 TB m _ CW5 mHMS‘I0mm%IV m m W. w .M H M n x w m W m U a IsP F 55mC& s. 2 m awasAulrl‘QM mG1|v c Ht D .HMM: 01c mm “ram InnW“3.6% mm nI\I- M smm mm Wm m...“ mw mm M m mw MW mm WM Mm m W mm 0mm _ now; nE!\b d| DA m m Fm mmI?ramIV b 9 > v 9+ * +G m. r r f K mm MM E u m..r.... x<5mc
