Download DN9200K10PCIE8T

H A R D W A R E
phase offset is between the CLK_ETH125 signal and the RXCLK signal and make a
synchronous domain change. We do the former because RGMII is very easy to put into an
elastic buffer.
All signals on RGMII are skew-matched on the board to within: 100ps
FPGA:
DCM is in system-synchronous mode with no phase adjustment
Worst clock-to-out
3.37
Worst setup time
0.097
Worst hold time
0.21
PHY: (clock measured at PHY pin)
clock-out
setup
valid
2ns
2ns
1.2ns
21.2 Configuration Registers
In order to read and write registers on the Vitesse part, you must implement a MDIO controller.
You will probably need to look at the Vitesse datasheet to see where register locations are and
IO timing, etc. This step is probably required, because the default register settings may or may
not be what you want.
If you do not implement the MDIO interface, then the default settings are used for the device.
This includes settings that are specified by multi-level inputs connected to resistors.
The CMODE options of the Ethernet PHYs has been set as follows
CMODE0 – 0100 (8.25 kΩ resistor)
CMODE1 – 0000 (0 Ω resistor)
CMODE2 – 0001 (2.2 kΩ resistor)
CMODE3 – 0000 (0 Ω resistor)
This results in the following settings
ADDR
=
CLKOUT
=
PAUSE
=
DOWNSHIFT =
SPEED
=
ACTIPHY® =
SKEW
=
00000
TRUE
00
FALSE
00
FALSE
11
MAC CALIBRATION MODE
DN9200K10PCIE8T User Guide
=
00
MDIO address
Drives the CLK_ETH_125 signal
I don‟t know
I don‟t know
Gigabit mode only
I don‟t know what this is.
This controls the MII timing. It probably won‟t work until you set this.
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