Download MPC106 PCI Bridge/Memory Controller Hardware Specifications

Freescale Semiconductor, Inc.
Electrical and Thermal Characteristics
Table 8. Output AC Timing Specifications
66 MHz
Num
Notes
Min
Max
Min
Max
2.0
—
2.0
—
1
13a SYSCLK to output valid for TS and
ARTRY
—
7.0
—
6.0
2, 3, 4
13b SYSCLK to output valid for all non-PCI
signals except TS, ARTRY, RAS[0–7],
CAS[0–7], and DWE[0-2]
—
7.0
—
6.0
2, 3, 5
14a SYSCLK to output valid (for RAS[0–7]
and CAS[0–7])
—
7.0
—
6.0
2, 3
14b SYSCLK to output valid for PCI signals
—
11.0
—
11.0
3, 6
15a SYSCLK to output invalid for all
non-PCI signals (output hold)
1.0
—
1.0
—
7, 10
15b SYSCLK to output invalid for PCI
signals (output hold)
1.0
—
1.0
—
7
18
SYSCLK to ARTRY high impedance
before precharge (output hold)
—
8.0
—
8.0
1
19
SYSCLK to ARTRY precharge enable
(0.4 *
tsysclk) + 2.0
—
(0.4 x
tsysclk) + 2.0
—
8, 1
21
SYSCLK to ARTRY high impedance
after precharge
—
(1.5 *
tsysclk) + 8.0
—
(1.5 x
tsysclk) + 8.0
8, 1
12
Freescale Semiconductor, Inc...
83.3 MHz
Characteristic
SYSCLK to output driven (output
enable time)
Notes:
These values are guaranteed by design and are not tested.
2 Output specifications are measured from 1.4 V on the rising edge of the appropriate clock to the TTL level (0.8
V or 2.0 V) of the signal in question. Both input and output timings are measured at the pin (see Figure 5).
3 The maximum timing specification assumes C = 50 pF.
L
4 The shared outputs TS and ARTRY require pull-up resistors to hold them negated when there is no bus master
driving them.
5 When the 106 is configured for asynchronous L2 cache SRAMs, the DWE[0–2] signals have a maximum
SYSCLK to output valid time of (0.5 x tPROC) + 8.0 ns (where tPROC is the 60x bus clock cycle time).
6 PCI 3.3 V signaling environment signals are measured from 1.65 V (Vdd ÷ 2) on the rising edge of SYSCLK to
VOH = 3.0 V or VOL = 0.3 V.
7 The minimum timing specification assumes C = 0 pF.
L
8 t
sysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). When the unit is given as tsysclk the
numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in
nanoseconds) of the parameter in question.
9 PCI devices which require more than the PCI-specified hold time of T = 0ns or systems where clock skew
h
approaches the PCI-specified allowance of 2ns may not work with the MPC106. For workarounds, see Motorola
application note Designing PCI 2.1-Compliant MPC106 Systems (order number AN1727/D).
1
MPC106 PCI Bridge/Memory Controller Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
11