1
Download Memory BIST Training Workbook
Transcript
Common BIST Variations Specifying Non-controlled Memory Ports Specifying Non-controlled Memory Ports ♦ Memory ports not to be controlled by BIST Controller ♦ Default assertion state is high ● Test bench holds the signal at the value opposite its assert state ♦ Default direction is input ● Except for “data_out” and “data_inout” ♦ Define in Library Model’s bist_definition section 3-21 MBISTArchitect:Common BIST Variations 3-32 Copyright © 2002 Mentor Graphics Corporation Memory BIST Training Workbook, 8.2002_1 March 2002
