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Table 3-5. Response to Snooped Bus Transactions (Continued)
Snooped Transaction
TT[0–4]
750 Response
Reserved
01111
—
Reserved
1XX11
—
3.6.5 Transfer Attributes
In addition to the address and transfer type signals, the 750 supports the transfer attribute
signals TBST, TSIZ[0–2], WT, CI, and GBL. The TBST and TSIZ[0–2] signals indicate
the data transfer size for the bus transaction.
The WT signal reflects the write-through status (the complement of the W bit) for the
transaction as determined by the MMU address translation during write operations. WT is
asserted for burst writes due to dcbf (flush) and dcbst (clean) instructions, and for snoop
pushes; WT is negated for ecowx transactions. Since the write-through status is not
meaningful for reads, the 750 uses the WT signal during read transactions to indicate that
the transaction is an instruction fetch (WT negated), or not an instruction fetch (WT
asserted).
The CI signal reflects the caching-inhibited/allowed status (the complement of the I bit) of
the transaction as determined by the MMU address translation even if the L1 caches are
disabled or locked. CI is always asserted for eciwx/ecowx bus transactions independent of
the address translation.
The GBL signal reflects the memory coherency requirements (the complement of the M bit)
of the transaction as determined by the MMU address translation. Castout and snoop
copy-back operations (TT[0–4] = 00110) are generally marked as nonglobal (GBL
negated) and are not snooped (except for reservation monitoring). Other masters, however,
may perform DMA write operations with this encoding but marked global (GBL asserted)
and thus must be snooped.
Table 3-6 summarizes the address and transfer attribute information presented on the bus
by the 750 for various master or snoop-related transactions.
Table 3-6. Address/Transfer Attribute Summary
Bus Transaction
A[0–31]
TT[0–4]
TBST
TSIZ[0–2]
GBL
WT
CI
Instruction fetch operations:
Burst (caching-allowed)
PA[0–28] || 0b000
01110
0
010
¬M
1
1*
Single-beat read
(caching-inhibited or cache
disabled)
PA[0–28] || 0b000
01010
1
000
¬M
1
¬I
PA[0–28] || 0b000
A1110
0
010
¬M
0
1*
Data cache operations:
Cache block fill (due to load or
store miss)
Chapter 3. Instruction and Data Cache Operation
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