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Table 3-6. Address/Transfer Attribute Summary (Continued)
Bus Transaction
A[0–31]
TT[0–4]
TBST
TSIZ[0–2]
GBL
WT
CI
Castout
(normal replacement)
CA[0–26] || 0b00000
00110
0
010
1
1
1*
Push (cache block push due to
dcbf/dcbst)
PA[0–26] || 0b00000
00110
0
010
1
0
1*
Snoop copyback
CA[0–26] || 0b00000
00110
0
010
1
0
1*
PA[0–31]
A1010
1
SSS
¬M
0
¬I
Single-beat write
PA[0–31]
(caching-inhibited, write-through,
or cache disabled)
00010
1
SSS
¬M
¬W
¬I
Data cache bypass operations:
Single-beat read
(caching-inhibited or cache
disabled)
Special instructions:
dcbz (addr-only)
PA[0–28] || 0b000
01100
0
010
0*
0
1*
dcbi (if HID0[ABE] = 1,
addr-only)
PA[0–26] || 0b00000
01100
0
010
¬M
0
1*
dcbf (if HID0[ABE] = 1,
addr-only)
PA[0–26] || 0b00000
00100
0
010
¬M
0
1*
dcbst (if HID0[ABE] = 1,
addr-only)
PA[0–26] || 0b00000
00000
0
010
¬M
0
1*
sync (if HID0[ABE] = 1,
addr-only)
0x0000_0000
01000
0
010
0
0
0
eieio (if HID0[ABE] = 1,
addr-only)
0x0000_0000
10000
0
010
0
0
0
stwcx. (always single-beat write) PA[0–29] || 0b00
10010
1
100
¬M
¬W
¬I
eciwx
PA[0–29] || 0b00
11100
EAR[28–31]
1
0
0
ecowx
PA[0–29] || 0b00
10100
EAR[28–31]
1
1
0
Notes:
PA = Physical address, CA = Cache address.
W,I,M = WIM state from address translation; ¬ = complement; 0*or 1* = WIM state implied by transaction type in table
For instruction fetches, reflection of the M bit must be enabled through HID0[IFEM].
A = Atomic; high if lwarx, low otherwise
S = Transfer size
Special instructions listed may not generate bus transactions depending on cache state.
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IBM PowerPC 740 / PowerPC 750 RISC Microprocessor User’s Manual