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ARTRY 7-14, 8-26
BG 7-4, 8-10
BR 7-4, 8-10
checkstop 8-42
CI 7-12
CKSTP_IN/CKSTP_OUT 7-22
CLK_OUT 7-29
configuration 7-3
COP/scan interface 8-44
data arbitration 8-10, 8-23
data transfer termination 8-26
DBB 7-16, 8-10, 8-24
DBDIS 7-19
DBG 7-15, 8-10
DBWO 7-16, 8-10, 8-25, 8-45
DHn/DLn 7-17
DPn 7-18
DRTRY 7-20, 8-26, 8-29
GBL 7-13
HRESET 7-23
INT 7-21, 8-42
L2 cache interface signals 7-25
L2ADDRn 7-25
L2CE 7-26
L2CLK_OUTA 7-27
L2CLK_OUTB 7-27
L2DATAn 7-25
L2DP 7-26
L2SYNC_IN 7-28
L2SYNC_OUT 7-27
L2WE 7-27
L2ZZ 7-28
MCP 7-21
PLL_CFGn 7-30
power and ground signals 7-30
QACK 7-24
QREQ 7-23, 8-43
reset 8-43
RSRV 7-24, 8-43
SMI 4-25, 7-21
SRESET 7-23, 8-43
system quiesce control 8-43
TA 7-19
TBEN 7-24
TBST 7-12, 8-16, 8-25
Index
TEA 7-20, 8-26, 8-30
TLBISYNC 7-25
transfer encoding 7-9
TS 7-6
TSIZn 7-11, 8-15
TTn 7-8, 8-15
WT 7-13
Single-beat transfer
reads with data delays, timing 8-35
reads, timing 8-33
termination 8-26
writes, timing 8-34
SLB management instructions A-28
SMI (system management interrupt) signal 425, 7-21
Snooping 3-25
Split-bus transaction 8-11
SPRGn registers 2-6
SRESET (soft reset) signal 7-23, 8-43
SRR0/SRR1 (status save/restore registers)
description 2-6
exception processing 4-7
Stage, definition 6-2
Stall, definition 6-3
Static branch prediction 6-9, 6-22
stwcx. 4-12
Superscalar, definition 6-3
sync 4-12
SYNC operation 3-27
Synchronization
context/execution synchronization 2-36
execution of rfi 4-11
memory synchronization instructions 2-59,
2-61, A-24
SYSCLK (system clock) signal 7-29
System call exception 4-21
System linkage instructions 2-55, 2-65
list of instructions A-26
System management interrupt 4-25, 10-1
System quiesce control signals (QACK/
QREQ) 8-43
System register unit
execution timing 6-27
latency, CR logical instructions 6-32
latency, system register instructions 6-31
Index - 9