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Table 7-3. Data Transfer Size (Continued)
TBST
TSIZ[0–2]
Transfer Size
Negated
100
4 bytes
Negated
101
5 bytes1
Negated
110
6 bytes1
Negated
111
7 bytes1
Note: 1Not generated by 750.
7.2.4.3 Transfer Burst (TBST)
The transfer burst (TBST) signal is an input/output signal on the 750.
7.2.4.3.1 Transfer Burst (TBST)—Output
Following are the state meaning and timing comments for the TBST output signal.
State Meaning
Asserted—Indicates that a burst transfer is in progress.
Negated—Indicates that a burst transfer is not in progress.
For external control instructions (eciwx and ecowx), TBST is used to
output bit 28 of the EAR, which is used to form the resource ID
(TBST||TSIZ0–TSIZ2).
Timing Comments Assertion/Negation—The same as A[0–31].
High Impedance—The same as A[0–31].
7.2.4.3.2 Transfer Burst (TBST)—Input
Following are the state meaning and timing comments for the TBST input signal.
State Meaning
Asserted/Negated—Used when snooping for single-beat reads (read
with no intent to cache).
Timing Comments Assertion/Negation—The same as A[0–31].
7.2.4.4 Cache Inhibit (CI)—Output
The cache inhibit (CI) signal is an output signal on the 750. Following are the state meaning
and timing comments for the CI signal.
State Meaning
Asserted—Indicates that a single-beat transfer will not be cached,
reflecting the setting of the I bit for the block or page that contains
the address of the current transaction.
Negated—Indicates that a burst transfer will allocate an 750 data
cache block.
Timing Comments Assertion/Negation—The same as A[0–31].
High Impedance—The same as A[0–31].
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IBM PowerPC 740 / PowerPC 750 RISC Microprocessor User’s Manual