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QuickWorks User Manual - Release 2008.2.1
Static Timing Analyzer
23.2.2.1.1.5 Processing False and Multi-Cycle Path in Timing Analyzing
This feature allows users to specify false and multi-cycle path in the design. The Static Timing
Analyzer excludes the false paths and adjusts the timing number of the multi-cycle paths in the
process of timing analyzing. To use this feature, specify the false and multi-cycle paths in the
.qcf file in the following format:
set_false_path [-from from_list] [-to to_list] [-through through_list]
set_multicycle_path <number of clock cycles> [-from from_list] [-to to_list]
[-through through_list]
NOTE: The from-to option provides the ability to specify the start and end nets of a false/multi-cycle
path. The through option provides the ability to specify the passing through nets for the false/multicycle path.
The designer can use the wildcard in the net names. The wildcards must be a suffix to the net
name.
Examples of qcf Commands in the .qcf file:
set_false_path
-from
set_multicycle_path
2
net_A
-from
-to
net_B
net_C
-to
net_D
-through
net_E
The false/multi-cycle path constraints are read into the SpDE internal database as part of the
loading process. When the designer runs the SpDE timing analyzing tools, the false/multi-cycle
path constraints are processed, and the results are reflected in the Static Timing Analyzer.
© 2008 QuickLogic Corporation
www.quicklogic.com
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