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Macro Library
QuickWorks User Manual - Release 2008.2.1
B.10 Shift Registers
In addition to extremely fast counters, the pASIC architecture can implement extremely fast
shift registers. In fact, the shift registers included in the macro library can operate at the
maximum logic cell toggle rate.
All of the shift registers offer a common clear control signal.
Table B-46: Macro Library Shift Registers
Macro
Description
Load
Enable
Clear
Direction
SHFT4
4-bit Shift Register w/ load, enable, clear
x
x
x
LSB->MSB
SHFT8
8-bit Shift Register w/ load, enable, clear
x
x
x
LSB->MSB
SHFT16
16-bit Shift Register w/ load, enable,
clear
x
x
x
LSB->MSB
BSHFT4
4-bit Bi-Directional Shift Register w/ load,
enable, clear
x
x
x
Both
BSHFT8
8-bit Bi-Directional Shift Register w/ load,
enable, clear
x
x
x
Both
BSHFT16
16-bit Bi-Directional Shift Register w/
load, enable, clear
x
x
x
Both
x
LSB->MSB
LSHFT2Q2
2-bit Dual Shift Register w/ clear
The unidirectional shifters have a common LOAD control signal, which causes the register to be
loaded synchronously from the D inputs when asserted. The bi-directional shifters have
common S0 and S1 control signals, which specify the function code.
Table B-47: Bi-Directional Shift Registers
S1
S0
Function
0
0
Holda Value
0
1
Shift Rightb (LSB-MSB)
1
0
Shift Leftc (MSB-LSB)
1
1
Loadd New Value
a. The hold function performs no action—the state of the register is
unchanged
b. The right shift function loads each bit from its RSI input
c. The left shift function loads each bit from its LSI input
d. The load function performs a parallel load from the D inputs.
LSHFT2Q2 is a dual shift register implemented in one pASIC3, QuickRAM, QuickPCI, or
Eclipse Logic Cell by wiring up the logic before the flip-flop to act as a master-slave latch.
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