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Application Note netX Design-In Guide netX 100/500 Hilscher Gesellschaft für Systemautomation mbH www.hilscher.com DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public Introduction 2/158 Table of Contents 1 Introduction.............................................................................................................................................4 1.1 About this Document......................................................................................................................4 1.2 Legal Notes ....................................................................................................................................5 1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 2 Copyright ........................................................................................................................................... 5 Important Notes................................................................................................................................. 5 Exclusion of Liability .......................................................................................................................... 5 Warranty............................................................................................................................................ 6 Export Regulation .............................................................................................................................. 6 netX100/500 Quick Start ........................................................................................................................7 2.1 Basic Circuit ...................................................................................................................................7 2.2 Ethernet Interface Circuits............................................................................................................25 2.2.1 Twisted Pair Two Channel............................................................................................................... 25 2.2.2 Twisted Pair Single Channel ........................................................................................................... 27 2.2.3 Fiber Optic with AFBR-5978Z.......................................................................................................... 29 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 AS-Interface .................................................................................................................................33 CANopen......................................................................................................................................35 CC-Link ........................................................................................................................................37 CompoNet ....................................................................................................................................39 DeviceNet.....................................................................................................................................41 PROFIBUS...................................................................................................................................43 MMC/SD-Card SPI-Circuit ...........................................................................................................45 UART Ù RS232...........................................................................................................................47 USB Device Mode........................................................................................................................49 USB Host Mode ...........................................................................................................................51 Embedded Trace Macrocell (ETM) ..............................................................................................53 LCD Interface ...............................................................................................................................55 3 Resource Overview ..............................................................................................................................59 3.1 rcX Operating System ..................................................................................................................59 3.2 Third Party Operating Systems....................................................................................................60 3.3 Memory Requirements of Hilscher Stacks...................................................................................61 4 Standard Circuits .................................................................................................................................62 4.1 RDY/RUN Pins, SYS LED............................................................................................................62 4.2 Secure EEPROM .........................................................................................................................65 4.3 Crystals, Clock generators ...........................................................................................................66 4.3.1 System Clock .................................................................................................................................. 66 4.3.2 Real Time Clock .............................................................................................................................. 67 4.4 4.5 Power On Reset and Reset In .....................................................................................................69 Debug and Test Interfaces...........................................................................................................70 4.5.1 JTAG Interface ................................................................................................................................ 70 4.5.2 ETM Interface.................................................................................................................................. 71 4.5.3 Boundary Scan................................................................................................................................ 72 4.6 External Memory ..........................................................................................................................74 4.6.1 FLASH Memory............................................................................................................................... 74 4.6.2 SDRAM ........................................................................................................................................... 81 4.7 Host Interface...............................................................................................................................84 4.7.1 4.7.2 4.7.3 4.7.4 4.8 4.9 DPM Mode ...................................................................................................................................... 85 Extension Bus Mode ....................................................................................................................... 93 Multiplex Mode ................................................................................................................................ 94 External pull-ups/pull-downs, unused signals.................................................................................. 96 UARTs..........................................................................................................................................97 USB ..............................................................................................................................................98 4.9.1 Device Mode ................................................................................................................................... 98 4.9.2 Host Mode ..................................................................................................................................... 100 4.10 Ethernet Interface.......................................................................................................................102 4.10.1 4.10.2 4.10.3 4.10.4 4.10.5 Twisted Pair................................................................................................................................... 102 Fiber Optic..................................................................................................................................... 105 Ethernet PHYs unused .................................................................................................................. 113 Ethernet Status LEDs .................................................................................................................... 114 Real Time Ethernet ....................................................................................................................... 115 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Introduction 3/158 4.11 Fieldbus Interface.......................................................................................................................118 4.11.1 4.11.2 4.11.3 4.11.4 4.11.5 4.11.6 4.11.7 4.12 4.13 4.14 4.15 4.16 4.17 4.18 A/D Converter ............................................................................................................................127 PWM Interface ...........................................................................................................................130 Encoder Interface.......................................................................................................................132 LCD Interface .............................................................................................................................134 Touch Panel Interface ................................................................................................................135 PIO .............................................................................................................................................137 Power Supply .............................................................................................................................138 4.18.1 4.18.2 4.18.3 4.18.4 5 AS interface Master ....................................................................................................................... 120 CANopen Interface ........................................................................................................................ 121 CC-Link Interface .......................................................................................................................... 122 CompoNet Interface ...................................................................................................................... 123 DeviceNet Interface ....................................................................................................................... 124 PROFIBUS Interface ..................................................................................................................... 125 Fieldbus Status LEDs .................................................................................................................... 126 Core Voltage Regulator ................................................................................................................. 138 Alternative Core Voltage Regulator ............................................................................................... 139 Common Supply Voltage Regulator 3.3 V ..................................................................................... 139 Voltage Regulator 5 V ................................................................................................................... 140 General Design Considerations........................................................................................................141 5.1 Thermal Behavior.......................................................................................................................141 5.1.1 Basics............................................................................................................................................ 141 5.1.2 Estimates....................................................................................................................................... 141 5.1.3 Rules of thumb .............................................................................................................................. 143 5.2 EMC behavior ............................................................................................................................144 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.3 Layer Stack ................................................................................................................................... 144 Decoupling capacitors ................................................................................................................... 145 Power Supply Input Filter .............................................................................................................. 146 Reset Lines ................................................................................................................................... 146 Clock Circuits ................................................................................................................................ 147 Ethernet Interface .......................................................................................................................... 147 Memory Bus .................................................................................................................................. 149 Planes ........................................................................................................................................... 149 Vias and Traces under the netX100/500 ...................................................................................151 6 Reference Section ..............................................................................................................................152 6.1 Crystals ......................................................................................................................................152 6.2 Memory Components.................................................................................................................152 6.3 List of Tables..............................................................................................................................155 6.4 List of Figures.............................................................................................................................156 7 Contacts ..............................................................................................................................................158 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Introduction 1 1.1 4/158 Introduction About this Document This document is directed to hardware developers creating a hardware design with a communication controller of the Hilscher netX family. It does not explain netX technology and features, which is covered by the corresponding Technical Data Reference Guides. It describes the standard circuitry around all netX interfaces like memory interface (SDRAM, FLASH) USB, UARTs, XMACs (Ethernet and field bus), LCD, as well as power supply, reset and clock circuits along with the standard netX I/O resources (PIOs, GPIOs) that have been assigned a default functionality at Hilscher. This includes Status LEDs, control signals and sync signals for RTE applications Although the system designer is basically completely free to select any available I/Os for I/O purposes, it is important that he complies with the standard port definitions, whenever loadable Firmware from Hilscher is to be used, as this kind of firmware necessarily assumes compliance with Hilscher standard assignments. Note: Designers should be aware, that not all components supported by netX hardware (e.g. parallel FLASH) are necessarily also supported by existing software / firmware or tools from Hilscher! Hence it is strongly recommended, to consult the feature table in the following chapter, to make sure that all desired hardware features of the planned design are eventually supported by the firmware that will run on the design. This applies not only, but particularly to customers planning to use loadable firmware from Hilscher instead of doing own firmware development. Resources that are currently not supported by loadable Firmware or where no drivers / code are yet available may still already be supported by existing Hilscher devices (e.g. Gateways). It is hence recommended to check with Hilscher Sales, if there is already an existing solution for your problem. Further, Hilscher offers several custom design services for netX hard- and software, as well as manufacturing services, providing an easy way to your custom product. For detailed information and quotes, please contact Hilscher Sales. Hilscher also offers a schematic review service, allowing your hardware design to be checked by netX experienced hardware engineers. Hilscher Sales will be happy to provide an individual quote for this service, after receiving your schematics (PDF format). Note: Before starting a design, it is strongly recommended, to consult the latest Errata Sheets (available on the Hilscher website www.hilscher.com) of the netX controllers! netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Introduction 1.2 1.2.1 5/158 Legal Notes Copyright © Hilscher, 2008-2012, Hilscher Gesellschaft für Systemautomation mbH All rights reserved. The images, photographs and texts in the accompanying material (user manual, accompanying texts, documentation, etc.) are protected by German and international copyright law as well as international trade and protection provisions. You are not authorized to duplicate these in whole or in part using technical or mechanical methods (printing, photocopying or other methods), to manipulate or transfer using electronic systems without prior written consent. You are not permitted to make changes to copyright notices, markings, trademarks or ownership declarations. The included diagrams do not take the patent situation into account. The company names and product descriptions included in this document may be trademarks or brands of the respective owners and may be trademarked or patented. Any form of further use requires the explicit consent of the respective rights owner. 1.2.2 Important Notes The user manual, accompanying texts and the documentation were created for the use of the products by qualified experts, however, errors cannot be ruled out. For this reason, no guarantee can be made and neither juristic responsibility for erroneous information nor any liability can be assumed. Descriptions, accompanying texts and documentation included in the user manual do not present a guarantee nor any information about proper use as stipulated in the contract or a warranted feature. It cannot be ruled out that the user manual, the accompanying texts and the documentation do not correspond exactly to the described features, standards or other data of the delivered product. No warranty or guarantee regarding the correctness or accuracy of the information is assumed. We reserve the right to change our products and their specification as well as related user manuals, accompanying texts and documentation at all times and without advance notice, without obligation to report the change. Changes will be included in future manuals and do not constitute any obligations. There is no entitlement to revisions of delivered documents. The manual delivered with the product applies. Hilscher Gesellschaft für Systemautomation mbH is not liable under any circumstances for direct, indirect, incidental or follow-on damage or loss of earnings resulting from the use of the information contained in this publication. 1.2.3 Exclusion of Liability The software was produced and tested with utmost care by Hilscher Gesellschaft für Systemautomation mbH and is made available as is. No warranty can be assumed for the performance and flawlessness of the software for all usage conditions and cases and for the results produced when utilized by the user. Liability for any damages that may result from the use of the hardware or software or related documents, is limited to cases of intent or grossly negligent violation of significant contractual obligations. Indemnity claims for the violation of significant contractual obligations are limited to damages that are foreseeable and typical for this type of contract. It is strictly prohibited to use the software in the following areas: netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Introduction 6/158 for military purposes or in weapon systems; for the design, construction, maintenance or operation of nuclear facilities; in air traffic control systems, air traffic or air traffic communication systems; in life support systems; in systems in which failures in the software could lead to personal injury or injuries leading to death. We inform you that the software was not developed for use in dangerous environments requiring fail-proof control mechanisms. Use of the software in such an environment occurs at your own risk. No liability is assumed for damages or losses due to unauthorized use. 1.2.4 Warranty Although the hardware and software was developed with utmost care and tested intensively, Hilscher Gesellschaft für Systemautomation mbH does not guarantee its suitability for any purpose not confirmed in writing. It cannot be guaranteed that the hardware and software will meet your requirements, that the use of the software operates without interruption and that the software is free of errors. No guarantee is made regarding infringements, violations of patents, rights of ownership or the freedom from interference by third parties. No additional guarantees or assurances are made regarding marketability, freedom of defect of title, integration or usability for certain purposes unless they are required in accordance with the law and cannot be limited. Warranty claims are limited to the right to claim rectification. 1.2.5 Export Regulation The delivered product (including the technical data) is subject to export or import laws as well as the associated regulations of different counters, in particular those of Germany and the USA. The software may not be exported to countries where this is prohibited by the United States Export Administration Act and its additional provisions. You are obligated to comply with the regulations at your personal responsibility. We wish to inform you that you may require permission from state authorities to export, re-export or import the product. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX100/500 Quick Start 2 2.1 7/158 netX100/500 Quick Start Basic Circuit This chapter describes the important basic parts of a netX100/500 circuit to use Hilscher loadable firmware. Some interfaces have a minimum circuit that have to be connected. Therefore, all interfaces circuit in this chapter shows the connection if they are unused. The following chapter described this interface circuits. RUN/RDY Let’s start with the circuit on RDY/RUN pins. These pins operate as input after reset. The first stage boot loader of the netX100/500 checks the logic level and enters certain boot modes. One important boot mode is the serial boot mode which will allow to (re-) flash the firmware over USB or RS232. To get the netX100/500 in this boot mode, the RDY pin has to be pulled-down to GND over a 1.27 kΩ resistor. A push button or pin header between the resistor and the RDY pin make it possible to activate this boot mode when it is necessary. For displaying system status, a yellow and green dual LED is recommended to connect antiparallel over to 220 Ω resistors to RDY and RUN pin. Two 15 kΩ pull-up resistors connected to 3.3 V stabilize the RDY and RUN lines in resting level. The following picture shows the basic RDY/RUN circuit for netX100/500. R1a Bootoptions: J2 J1 Boot from the first Loader found in FLASH at Memory Controller serial EPROM at SPI - I2C - MMC W20 J2 220 220 RDY 15k R2a 15k +3.3V J1 Serial boot mode (UART0 or USB) RDY yellow J2 J1 Dual-Port Memory boot mode W21 J2 J1 J2 R2b 1.27k netX100/500 1.27k RUN RUN green R1b J1 Extension Bus boot mode GND Figure 1: netX100/500 RDY/RUN Basic Circuit More about RDY/RUN circuit can be found on: Æ Page 62 chapter 4.1 RDY/RUN Pins, SYS LED netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX100/500 Quick Start 8/158 SPI Flash Memory The Hilscher loadable firmware is always stored in flash memory, which is connected via SPI with the netX100/500. SPI_MISO SPI_MOSI SPI_CLK SPI_CS0 SPI_CS1 netX 100 SPI_CS2 netX 500 AT45DB321 W17 W16 1 W18 2 V18 3 V17 4 SI SO CLK GND RESET VCC WP CS 8 +3.3V 7 6 5 V16 0.1 µF GND GND PORn Figure 2: netX100/500 SPI Flash More about SPI, Flash Memory, MMC/SD-Card circuit can be found on: Æ Page 45 chapter 2.9 MMC/SD-Card SPI-Circuit Æ Page 61 chapter 3.3 Memory Requirements of Hilscher Stacks Æ Page 74 chapter 4.6.1.1 SPI FLASH Æ Page 75 chapter 4.6.1.2 MMC/SD Card Æ Page 76 chapter 4.6.1.3 Parallel FLASH Secure EEPROM The Secure EEPROM connected via I²C-Bus with netX100/500 hold licensing information, MAC address and other information. +3.3V AT88SC0104C 8 0.1 µF I2C_SCL I2C_SDA 7 W15 6 W14 5 VCC NC NC NC SCL NC SDA GND 1 2 3 4 netX100/500 GND Figure 3: netX100/500 Secure Memory Basic Circuit More about Secure EEPROM and I²C-Bus circuit can be found on: Æ Page 65 chapter 4.2 Secure EEPROM netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX100/500 Quick Start 9/158 Base Clock The netX100/500 uses an internal oscillator along with an external crystal for generating 25 MHz base clock. + 1.5V netX 500 netX 100 OSC-VDDC OSC-VSS OSC-XTI V2 W2 OSC-XTO V1 W1 GND 25 MHz 22 pF 22 pF GND GND Figure 4: netX100/500 System Oscillator Circuit More about base clock circuit can be found on: Æ Page 66 Chapter 4.3 Crystals, Clock generators Real Time Clock The netX500 real time clock is not necessary for the basic circuit and has to be connected like the netX100 Pins to 1.5 V and 3.3 V. netX 500 netX 100 Backup RAM RTC-VDDIO + 3.3V W7 + 3.3V + 1.5V 16 kByte RTC-POK RTC-VDDC RTC-XTI AA7 RTC-XTO Y7 AA6 Y6 GND Figure 5: netX100/500 RTC Not Used in Basic Circuit More about real time clock circuit can be found on: Æ Page 66 Chapter 4.3 Crystals, Clock generators netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX100/500 Quick Start 10/158 Reset The netX100 and netX500 provide two inputs for reset signals, the Power On Reset (PORn) and the Reset In (RSTINn). While the use of the RSTINn is optional, the Power On Reset is mandatory. + 3.3V To other parts such as Flash or JTAG connector. C18 RSTIN + 3.3V 3 100nF 1 GND VCC RESET out 2 W19 POR netX500 netX100 GND 1nF MAX809SEUR-T GND Figure 6: netX100/500 Reset Circuit More about reset circuit can be found on: Æ Page 69 Chapter 4.4 Power On Reset and Reset In USB The device mode is the commonly used mode of the netX USB interface and allows to connect the netX to a PC (in serial boot mode), which can then download and flash firmware, read and modify register values and run hardware test applications by the help of freely available software tools from Hilscher. 3.3V USB_VDDIO USB_VDDC D18 C19 AA13 1 VBUS 1.5k GPIO12 1.5V USB_DPOS B20 24 3 D+ 2 1 D- 3 4 SN65220D Transient Suppressor USB_DNEG B19 24 2 Receptacle „B“ USB_VSS netX100/500 A19 4 GND GND Figure 7: netX100/500 USB DOWN Stream Port (Device Mode) More about USB circuit can be found on: Æ Page 69 Chapter 4.4 Power On Reset and Reset In netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX100/500 Quick Start 11/158 UART0 For using the serial boot mode on UBS port with unconnected UART0, the pin AA19 (UART0_RXD) and pin AA18 (UART0_CTS#) have to be connected with 10 kΩ pull-up resistors to +3.3 V. +3.3V GPIO03 / UART0_RTSn GPIO00 / UART0_RXD GPIO02 / UART0_CTSn Y18 10k Y19 10k GPIO01 / UART0_TXD AA19 AA18 netX100 netX500 Figure 8: netX100/500 UART0 Unused More about UART circuits can be found on: Æ Page 97 Chapter 4.8 UARTs AD-Converter ADU0 If the ADC is not used, it must still be connected to the power supply AA5 ADO_IN0 Y5 ADO_IN1 W5 ADO_IN2 V5 ADO_IN3 +3V3 W6 +3V3 AD0_VDDIO V6 AD0_VREFP ADU1 AA4 GND AD0_VREFM Y4 AD0_VSS Y3 AD1_IN0 W3 AD1_IN1 V4 AD1_IN2 U5 AD1_IN3 W4 +3V3 AD1_VDDIO AA3 AD1_VREFP V3 AD1_VREFM U4 AD1_VSS GND MICRO-NETX500-2210.000 GND Figure 9: Unused ADC Basic Circuit More about ADC-Converter circuits can be found on: Æ Page 127 chapter 4.12 A/D Converter netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX100/500 Quick Start 12/158 SDRAM The standard Hilscher loadable firmware uses 8 MB SDRAM. The following figure shows the connection of ISSI SDRAM with 86 pin TSOP package (IS42S32200C1) MEM_D[00:31] netX100/500 K1-F MEM_D0 MEM_D1 MEM_D2 MEM_D3 MEM_D4 MEM_D5 MEM_D6 MEM_D7 MEM_D8 MEM_D9 MEM_D10 MEM_D11 MEM_D12 MEM_D13 MEM_D14 MEM_D15 MEM_D16 MEM_D17 MEM_D18 MEM_D19 MEM_D20 MEM_D21 MEM_D22 MEM_D23 MEM_D24 MEM_D25 MEM_D26 MEM_D27 MEM_D28 MEM_D29 MEM_D30 MEM_D31 MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12 MEM_A13 MEM_A14 MEM_A15 MEM_A16 MEM_A17 MEM_A18 MEM_A19 MEM_A20 MEM_A21 MEM_A22 MEM_A23 MEMSR_SC0 MEMSR_SC1 MEMSR_SC2 MEMSR_OE MEMSR_WE G4 H4 J4 K4 M4 N4 P4 R4 G3 H3 J3 K3 M3 N3 P3 R3 D1 D2 C1 C2 B2 B3 A3 A4 B4 C3 C4 D3 D4 E3 E4 F3 E2 E1 F2 F1 G2 G1 H2 H1 J2 J1 K2 L3 M1 M2 N1 N2 P1 P2 R1 R2 T1 T2 U1 U2 MEM_D00 MEM_D01 MEM_D02 MEM_D03 MEM_D04 MEM_D05 MEM_D06 MEM_D07 MEM_D08 MEM_D09 MEM_D10 MEM_D11 MEM_D12 MEM_D13 MEM_D14 MEM_D15 MEM_D16 MEM_D17 MEM_D18 MEM_D19 MEM_D20 MEM_D21 MEM_D22 MEM_D23 MEM_D24 MEM_D25 MEM_D26 MEM_D27 MEM_D28 MEM_D29 MEM_D30 MEM_D31 MEM_A[00:23] 8MB SRAM C201 25 26 27 60 61 62 63 64 65 66 24 21 69 MEM_A13 MEM_A14 22 23 MEM_A00 MEM_A01 MEM_A02 MEM_A03 MEM_A04 MEM_A05 MEM_A06 MEM_A07 MEM_A08 MEM_A09 MEM_A10 MEM_A11 MEM_A12 16 71 28 59 20 19 18 17 68 67 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 0 A 4M BS0 BS1 DQM0 DQM1 DQM2 DQM3 CS# RAS# CAS# WE# CLK CKE MEM_A16 MEM_A17 K1 R5 T5 T4 T3 E5 F5 G5 H5 J5 F4 VDD1 VDD2 VDD3 VDD4 VSS1 VSS2 VSS3 VSS4 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 A DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 P5 MEM_DQM0 N5 MEM_DQM1 M5 MEM_DQM2 K5 MEM_DQM3 MEMDR_CS MEMDR_RAS MEMDR_CAS MEMDR_WE MEMDR_CLK MEMDR_CKE +3V3 RAM 512k x 32 x 4 MEM_A00 MEM_A01 MEM_A02 MEM_A03 MEM_A04 MEM_A05 MEM_A06 MEM_A07 MEM_A08 MEM_A09 MEM_A10 MEM_A11 MEM_A12 1 15 29 43 44 58 72 86 3 9 35 41 49 55 75 81 6 12 32 38 46 52 78 84 2 4 5 7 8 10 11 13 74 76 77 79 80 82 83 85 31 33 34 36 37 39 40 42 45 47 48 50 51 53 54 56 1 0603 C202 100nF 2 1 0603 C203 100nF 2 GND +3V3 1 0603 2 C204 100nF 1 0603 C205 100nF 2 GND MEM_D00 MEM_D01 MEM_D02 MEM_D03 MEM_D04 MEM_D05 MEM_D06 MEM_D07 MEM_D08 MEM_D09 MEM_D10 MEM_D11 MEM_D12 MEM_D13 MEM_D14 MEM_D15 MEM_D16 MEM_D17 MEM_D18 MEM_D19 MEM_D20 MEM_D21 MEM_D22 MEM_D23 MEM_D24 MEM_D25 MEM_D26 MEM_D27 MEM_D28 MEM_D29 MEM_D30 MEM_D31 SDRAM64M32-3V3I7T MICRO-NETX500-2210.000 Figure 10: netX100/500 Connection of 8MB SDRAM More about SDRAM circuits can be found on: Æ Page 81 Chapter 4.6.2 SDRAM netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX100/500 Quick Start 13/158 Ethernet The basic circuit assumes that Ethernet is not used. Figure 11 shows the netX100/500 PHY power connection, if the Ethernet interface is not used. +3V3 K1-E J20 +3V3 PHY_VDDIOAT F18 PHY_VDDIOAC 1 0402 C301 100nF 2 PHY_VDDCAP +1V5 F17 +1V5 1 0402 J21 PHY_VSSAT E18 PHY_VSSACP PHY0_VDDCART PHY0_TXP C302 100nF 2 GND H17 +1V5 G21 G20 PHY0_TXN H21 PHY0_RXP PHY0_RXN H20 H18 PHY0_VSSAR H19 PHY0_VSSAT1 G18 PHY0_VSSAR2 PHY1_VDDCART PHY1_TXP GND D20 +1V5 F20 F21 PHY1_TXN E20 PHY1_RXP PHY1_RXN E21 D19 PHY1_VSSAR E19 PHY1_VSSAT1 F19 PHY1_VSSAT2 G19 PHY_EXTRES G17 PHY_ATP GND R3012 1 0603 12.4k MICRO-NETX500-2210.000 GND Figure 11: netX100/500 Ethernet Not Used More about Ethernet circuits can be found on: Æ Page 25 Chapter 2.2 Ethernet Interface Æ Page 102 Chapter 4.10 Ethernet Interface netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX100/500 Quick Start 14/158 Host Interface For the basic circuit, only the TCLK A11 pin has to be connected with a pull up resistor to ground. All other pins have to be connected to the companion chip. R3022 1 0603 10k A11 HIFPIO_83 HIFPIO_82 HIFPIO_81 HIFPIO_78 HIFPIO_77 HIFPIO_76 HIFPIO_75 HIFPIO_74 HIFPIO_32 HIFPIO_34 HIFPIO_33 HIFPIO_39 HIFPIO_38 HIFPIO_37 HIFPIO_42 HIFPIO_41 EXT_D0 EXT_D1 EXT_D2 EXT_D3 EXT_D4 EXT_D5 EXT_D6 EXT_D7 EXT_D8 EXT_D9 EXT_D10 EXT_D11 EXT_D12 EXT_D13 EXT_D14 EXT_D15 HIFPIO_73 HIFPIO_70 HIFPIO_69 HIFPIO_66 HIFPIO_65 HIFPIO_64 HIFPIO_61 HIFPIO_60 HIFPIO_57 HIFPIO_56 HIFPIO_53 HIFPIO_50 HIFPIO_49 HIFPIO_48 HIFPIO_54 HIFPIO_55 HIFPIO_58 HIFPIO_59 HIFPIO_62 HIFPIO_63 HIFPIO_67 HIFPIO_68 HIFPIO_71 HIFPIO_72 EXT_A0 EXT_A1 EXT_A2 EXT_A3 EXT_A4 EXT_A5 EXT_A6 EXT_A7 EXT_A8 EXT_A9 EXT_A10 EXT_A11 EXT_A12 EXT_A13 EXT_A14 EXT_A15 EXT_A16 EXT_A17 EXT_A18 EXT_A19 EXT_A20 EXT_A21 EXT_A22 EXT_A23 HIFPIO_51 HIFPIO_80 HIFPIO_79 HIFPIO_84 HIFPIO_43 HIFPIO_35 HIFPIO_45 HIFPIO_44 HIFPIO_52 HIFPIO_46 HIFPIO_47 EXT_CS0 EXT_CS1 EXT_CS2 EXT_CS3 EXT_BHE EXT_ALE EXT_WRL EXT_WRH EXT_RD EXT_RDY EXT_IRQ HIFPIO_36 HIFPIO_40 TCLK C5 B5 A5 C6 B6 A6 C7 B7 A18 B17 A17 C16 B16 A16 C15 B15 A7 C8 B8 C9 B9 A9 C10 B10 C11 B11 C12 C13 B13 A13 D12 E12 D11 E11 D10 E10 D9 E9 D8 E8 D13 E6 D6 D5 A14 C17 C14 B14 E13 D14 E14 D17 E16 MICRO-NETX500-2210.000 GND Figure 12: Unused Host Interface If the Host Interface is not connected, it is recommended to configure the pins in PIO mode (output) by software or connects pull-up/pull-down resistors. The reason is that the Host Interface pins are floating, because they do not have internal pull-up or pulldown resistor. Note: More about Host Interface circuits can be found on: Æ Page 84 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public Chapter 4.7 © Hilscher, 2008-2012 netX100/500 Quick Start 15/158 Host Interface netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX100/500 Quick Start 16/158 Power Supply 3.3 V The following figure shows a power supply circuit for 9-24 V input voltage and 3.3 V/3 A output. The main part of the power supply is the MIC2198. 9V-24V power in line 9V-24V 1 C401 1 1210 10uF C402 2 C403 1 1210 10uF 1210 10uF 2 2 T501 GND C405 1 6 VIN 2 EN/UVLO 0805 100nF K401 2 0805 8 S 1 GND 1 2 5 6 R404 1 FB GND R405 1 PMEG4005 4 10uH 4A 3 4 GND C408 1 2 5 R406 0.018 R407 +3V3 2 4.7k 2 3 1 2.2k 0603 0603 2 1 2 100nF 4 2 MIC2198 13 9 STEPDOWN-MIC2198YML 2 6 5 0805 10uF 0603 100nF VOUT GND1 1 PMEG4005 2 C406 2 G C404 R402 5 6 1 3 0603 2.2nF 1 3 2 11 K402 CSH C407 1 10 D1 D2 D3 FDC5612 D4 LDS 4 G 0603 1 COMP VSW S 3 4 R403 BST 1 2 5 6 1206 1 Synchronous Buck Controller FDC5612 GND 12 HSD 7 VDD D1 D2 D3 D4 R408 1 1.5k C409 0805 22uF 2 2 GND Figure 13: +3.3 V Power Supply Standard Circuit Power Supply 1.5 V Core The Hilscher standard circuit uses the FAN2001 to produce the 1.5 V core voltage. R410 +3V3 T402 1 EN FB 2 1 2 3.3µH IND-LSFS3.3UA1.18 C410 0805 22uF 2 SW PGND AGND 4 7 FAN2001 1 0603 3 VIN 6 R411 1.8k 1 2 1 0603 1 C411 0805 22uF R412 2 1.96k 2 GND Figure 14: 1.5 V Core Voltage Regulator netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX100/500 Quick Start 17/158 More about power supply circuits can be found on: Æ Page 138 Chapter 4.18 Power Supply netX100/500 Power Supply Pins The following figure shows the connection of netX100/500 to the power supply. +3V3 +1V5 K1-N +3V3 A15 VDDH_1 A10 VDDH_2 A8 VDDH_3 +1V5 K17 VDDC_1 K18 VDDC_2 T17 VDDC_3 T18 VDDC_4 U3 VDDC_5 C20 VDDC_6 C21 VDDC_7 D21 VDDC_8 J17 VDDC_9 J18 VDDC_10 +1V5 A12 VDDC_11 B12 VDDC_12 VDDIO_1 VDDIO_2 VDDIO_3 VDDIO_4 VDDIO_5 VDDIO_6 VDDIO_7 VDDIO_8 VDDIO_9 VDDIO_10 VDDIO_11 VDDIO_12 VDDIO_13 D7 +3V3 E7 D15 E15 L17 L18 U15 V15 U7 V7 U6 L4 L5 A1 VDDIO_14 B1 VDDIO_15 +3V3 1 1 0603 C412 0603 100nF 2 C417 100nF 1 0805 C418 10uF 2 2 +1V5 L20 VDDC_13 L21 VDDC_14 A21 +3V3 VDDIO_16 B21 VDDIO_17 1 1 0603 C413 0603 100nF 2 C419 100nF 2 +1V5 Y12 VDDC_15 AA12 VDDC_16 1 0805 2 C414 10uF 1 0603 Y21 +3V3 VDDIO_18 AA21 VDDIO_19 C415 1 0603 100nF 2 1 100nF 2 +1V5 0603 C420 L1 VDDC_17 L2 VDDC_18 1 0603 100nF GND J10 VSS_1 J11 VSS_2 J12 VSS_3 K9 VSS_4 K13 VSS_5 M9 VSS_6 M13 VSS_7 N10 VSS_8 N11 VSS_9 N12 VSS_10 E17 VSS_11 J19 VSS_12 K21 VSS_13 A2 VSS_14 A20 VSS_15 Y20 VSS_16 AA20 VSS_17 C421 10uF 2 Y1 +3V3 VDDIO_20 AA1 VDDIO_21 C416 2 1 0805 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 C422 100nF 2 Y2 GND AA2 J9 J13 K10 K11 K12 L9 L10 L11 L12 L13 M10 M11 M12 N9 N13 MICRO-NETX500-2210.000 GND GND Figure 15: netX100/500 Power Connection Pull-Down Resistors The basic circuit does not use the pins D16 WDGACT (watchdog active) and B18 CLKOUT (clock out) and have always connected to GND over a 10 kΩ resistor in this case. Not Connected Pins All other pin of netX100/500 has not to be connected. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 J I H G F E D C B A 1 Checked Edited GND 2 MICRO-NETX500-2210.000 SPI_MISO SPI_MOSI SPI_CLK SPI_CS0 SPI_CS1 SPI_CS2 K1-J W17 W16 W18 V18 V17 V16 netX100/500 SPI Date Name Date Name GND VCC >= 2.93V Q101 RESET 2 24.10.2011 Matthias Melzer 3 2 POR# MAX809SEUR-T VOLTAGE-RESET-MAX809SEUR-T 1 3 Power On Reset C105 0603 100nF 1 +3V3 W14 I2C_SDA W15 I2C_SCL MICRO-NETX500-2210.000 K1-H netX100/500 I²C 4 8 3 C102 GND 2 0603 100nF 1 +3V3 GND VCC WP# 7 6 5 22pF 2 1 22pF 2 C107 1 C106 AT45DB321C-CNU RESET# MOSI MISO SCK CS# ROM 32Mbit C103 2 1 4 www.hilscher.com 5 C104 K1-A GND GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 IRQ/GPIO15 A19 1 OSC_XTO RSTOUT V19 7 8 9 RUN/RDY_USB_SEC-MEM_SPI-FLASH 6 10 1 2 1 1 1.27k 11 R103 XJLE2SG 1 GND 2 1.27k 12 R104 XJLE2SG X103 1 RDY green 3 RUN yellow LEDSYG 4 2 P101 RDY / RUN status LEDs PE 1 VBUS 2 D3 D+ 4 GND 5 SHIELD1 6 SHIELD2 XUSBB4BW X101 DD+ 14 13 14 Page of Page Dual-Port Memory boot mode 220 0603 R1062 RDY 1 220 0603 GND R1052 RUN 1 1 2 15k 13 Service interface USB-B connector X102 RUN 2 R102 +3V3 12 1 2 15k R101 +3V3 24 2 D+ R115 0603 24 0603 R1142 D- USB- 1 USB+ 1 11 SN65220DBVT R112 1.5k R111 10k R110 RDY GND 2 5 GND A B 6 4 2 Serial boot mode GND 1 2 GND 10k 0603 R1082 1 10k R109 GND MICRO-NETX500-2210.000 POR RSTIN B18 GND 2 1 +3V3 2 1nF C108 POR# W19 C18 CLKOUT 10k 0603 R1072 1 1 +3V3 10 2 0603 W1 OSC_XTI V2 OSC_VDDC GND W2 OSC_VSS +3V3 +1V5 V1 RUN W21 RUN RDY W20 RDY D16 B19 USB- B20 USB+ USB_DPOS USB_DNEG MICRO-NETX500-2210.000 USB_VSS D18 USB_VDDIO C19 USB_VDDC K1-L AA19 Y19 AA18 Y18 AA17 Y17 AA16 Y16 AA15 Y15 AA14 Y14 AA13 Y13 W13 V13 netX100/500 USB MICRO-NETX500-2210.000 WDGACT K1-K K19 TEST T19 TMC1 L19 TMC2 K20 TACT_TRST 9 netX100/500 UART 8 netX100/500 RUN/RDY Clock +1V5 +3V3 7 netX100/500 basic circuit ABM7-25M G101 GND 2 0603 100nF 1 +3V3 Flash memory for firmware AT88SC0104C-SU EEPROM-AT88SC0104C-SU GND VCC ROM 1k C101 5 SDA 6 SCL 1 8 2 4 6 Secure memory for license / MAC-address 5 Hilscher Gesellschaft für Systemautomatiom mbH GND 4 0603 3 25MHz 0603 0603 2 0603 0603 0603 0603 0603 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public 0603 1 5 1 POR# J I H G F E D C B A netX100/500 Quick Start 18/158 Basic Circuit Overview Figure 16: netX100/500 Basic Circuit RDY/RUN USB SEC-MEM SPI-FLASH © Hilscher, 2008-2012 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public J I H G F E D C B A 1 Checked Edited 1 3 Date Name Date MEMDR_CS MEMDR_RAS MEMDR_CAS MEMDR_WE MEMDR_CLK MEMDR_CKE 2 24.10.2011 Matthias Melzer MICRO-NETX500-2210.000 Name K1 R5 T5 T4 T3 E2 E1 F2 F1 G2 G1 H2 H1 J2 J1 K2 L3 M1 M2 N1 N2 P1 P2 R1 R2 T1 T2 U1 U2 G4 H4 J4 K4 M4 N4 P4 R4 G3 H3 J3 K3 M3 N3 P3 R3 D1 D2 C1 C2 B2 B3 A3 A4 B4 C3 C4 D3 D4 E3 E4 F3 E5 F5 G5 H5 J5 F4 P5 MEM_DQM0 N5 MEM_DQM1 M5 MEM_DQM2 K5 MEM_DQM3 MEMSR_SC0 MEMSR_SC1 MEMSR_SC2 MEMSR_OE MEMSR_WE MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12 MEM_A13 MEM_A14 MEM_A15 MEM_A16 MEM_A17 MEM_A18 MEM_A19 MEM_A20 MEM_A21 MEM_A22 MEM_A23 MEM_D0 MEM_D1 MEM_D2 MEM_D3 MEM_D4 MEM_D5 MEM_D6 MEM_D7 MEM_D8 MEM_D9 MEM_D10 MEM_D11 MEM_D12 MEM_D13 MEM_D14 MEM_D15 MEM_D16 MEM_D17 MEM_D18 MEM_D19 MEM_D20 MEM_D21 MEM_D22 MEM_D23 MEM_D24 MEM_D25 MEM_D26 MEM_D27 MEM_D28 MEM_D29 MEM_D30 MEM_D31 K1-F 3 netX100/500 Memory 2 5 4 www.hilscher.com 5 6 7 6 MEMORY 7 22 23 MEM_A16 MEM_A17 16 71 28 59 20 19 18 17 68 67 25 26 27 60 61 62 63 64 65 66 24 21 69 8 9 0 A 4M A DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VDD1 VDD2 VDD3 VDD4 VSS1 VSS2 VSS3 VSS4 9 SDRAM64M32-3V3I7T DQM0 DQM1 DQM2 DQM3 CS# RAS# CAS# WE# CLK CKE BS0 BS1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 RAM 512k x 32 C201 8MB SRAM MEM_A00 MEM_A01 MEM_A02 MEM_A03 MEM_A04 MEM_A05 MEM_A06 MEM_A07 MEM_A08 MEM_A09 MEM_A10 MEM_A11 MEM_A12 MEM_D[00:31] 8 netX100/500 basic circuit MEM_A[00:23] Hilscher Gesellschaft für Systemautomatiom mbH MEM_A16 MEM_A17 MEM_A00 MEM_A01 MEM_A02 MEM_A03 MEM_A04 MEM_A05 MEM_A06 MEM_A07 MEM_A08 MEM_A09 MEM_A10 MEM_A11 MEM_A12 MEM_D00 MEM_D01 MEM_D02 MEM_D03 MEM_D04 MEM_D05 MEM_D06 MEM_D07 MEM_D08 MEM_D09 MEM_D10 MEM_D11 MEM_D12 MEM_D13 MEM_D14 MEM_D15 MEM_D16 MEM_D17 MEM_D18 MEM_D19 MEM_D20 MEM_D21 MEM_D22 MEM_D23 MEM_D24 MEM_D25 MEM_D26 MEM_D27 MEM_D28 MEM_D29 MEM_D30 MEM_D31 4 10 2 4 5 7 8 10 11 13 74 76 77 79 80 82 83 85 31 33 34 36 37 39 40 42 45 47 48 50 51 53 54 56 3 9 35 41 49 55 75 81 6 12 32 38 46 52 78 84 1 15 29 43 44 58 72 86 10 1 2 0603 1 2 0603 11 100nF C204 100nF C202 11 100nF C205 12 GND 2 0603 1 100nF C203 +3V3 GND 2 0603 1 +3V3 12 13 MEM_D00 MEM_D01 MEM_D02 MEM_D03 MEM_D04 MEM_D05 MEM_D06 MEM_D07 MEM_D08 MEM_D09 MEM_D10 MEM_D11 MEM_D12 MEM_D13 MEM_D14 MEM_D15 MEM_D16 MEM_D17 MEM_D18 MEM_D19 MEM_D20 MEM_D21 MEM_D22 MEM_D23 MEM_D24 MEM_D25 MEM_D26 MEM_D27 MEM_D28 MEM_D29 MEM_D30 MEM_D31 13 14 Page of Page 14 5 2 J I H G F E D C B A netX100/500 Quick Start 19/158 Figure 17: netX100/500 Basic Circuit SDRAM © Hilscher, 2008-2012 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public J I H G F E D C B 1 Checked Edited 3 Date Name Date Name H20 F20 E21 24.10.2011 Matthias Melzer 3 G19 PHY_EXTRES G17 PHY_ATP D19 PHY1_VSSAR E19 PHY1_VSSAT1 F19 PHY1_VSSAT2 PHY1_RXN GND 1 12.4k 0603 R3012 GND D20 +1V5 F21 PHY1_TXN E20 PHY1_RXP PHY1_TXP PHY1_VDDCART MICRO-NETX500-2210.000 2 G21 H18 PHY0_VSSAR H19 PHY0_VSSAT1 G18 PHY0_VSSAR2 PHY0_RXN GND H17 +1V5 G20 PHY0_TXN H21 PHY0_RXP PHY0_TXP PHY0_VDDCART J21 PHY_VSSAT E18 PHY_VSSACP F17 +1V5 PHY_VDDCAP J20 +3V3 PHY_VDDIOAT F18 PHY_VDDIOAC K1-E netX100/500 Ethernet 2 GND 2 0402 1 5 6 7 8 9 10 11 2 0402 1 +1V5 100nF C302 4 www.hilscher.com 5 Hilscher Gesellschaft für Systemautomatiom mbH 100nF C301 +3V3 K1-I Y7 AA7 W7 MICRO-NETX500-2210.000 RTC_XTO RTC_XTI RTC_POK AA6 RTC_VDDIO Y6 RTC_VDDC AA5 ADO_IN0 Y5 ADO_IN1 W5 ADO_IN2 V5 ADO_IN3 MICRO-NETX500-2210.000 V3 AD1_VREFM U4 AD1_VSS GND W4 +3V3 AD1_VDDIO AA3 AD1_VREFP Y3 AD1_IN0 W3 AD1_IN1 V4 AD1_IN2 U5 AD1_IN3 AA4 GND AD0_VREFM Y4 AD0_VSS W6 +3V3 AD0_VDDIO V6 AD0_VREFP K1-D 6 7 8 9 ADC/HOST-INTERFACE/PHY/RTC GND +3V3 netX100/500 A/D-Converter GND +3V3 netX100/500 basic circuit +1V5 netX100/500 Real-Time-Clock 10 GND K1-O 12 13 11 10k 0603 R3022 1 A11 HIFPIO_36 HIFPIO_40 12 MICRO-NETX500-2210.000 TCLK EXT_CS0 EXT_CS1 EXT_CS2 EXT_CS3 EXT_BHE EXT_ALE EXT_WRL EXT_WRH EXT_RD EXT_RDY EXT_IRQ EXT_A0 EXT_A1 EXT_A2 EXT_A3 EXT_A4 EXT_A5 EXT_A6 EXT_A7 EXT_A8 EXT_A9 EXT_A10 EXT_A11 EXT_A12 EXT_A13 EXT_A14 EXT_A15 EXT_A16 EXT_A17 EXT_A18 EXT_A19 EXT_A20 EXT_A21 EXT_A22 EXT_A23 HIFPIO_73 HIFPIO_70 HIFPIO_69 HIFPIO_66 HIFPIO_65 HIFPIO_64 HIFPIO_61 HIFPIO_60 HIFPIO_57 HIFPIO_56 HIFPIO_53 HIFPIO_50 HIFPIO_49 HIFPIO_48 HIFPIO_54 HIFPIO_55 HIFPIO_58 HIFPIO_59 HIFPIO_62 HIFPIO_63 HIFPIO_67 HIFPIO_68 HIFPIO_71 HIFPIO_72 HIFPIO_51 HIFPIO_80 HIFPIO_79 HIFPIO_84 HIFPIO_43 HIFPIO_35 HIFPIO_45 HIFPIO_44 HIFPIO_52 HIFPIO_46 HIFPIO_47 EXT_D0 EXT_D1 EXT_D2 EXT_D3 EXT_D4 EXT_D5 EXT_D6 EXT_D7 EXT_D8 EXT_D9 EXT_D10 EXT_D11 EXT_D12 EXT_D13 EXT_D14 EXT_D15 HIFPIO_83 HIFPIO_82 HIFPIO_81 HIFPIO_78 HIFPIO_77 HIFPIO_76 HIFPIO_75 HIFPIO_74 HIFPIO_32 HIFPIO_34 HIFPIO_33 HIFPIO_39 HIFPIO_38 HIFPIO_37 HIFPIO_42 HIFPIO_41 D17 E16 D13 E6 D6 D5 A14 C17 C14 B14 E13 D14 E14 A7 C8 B8 C9 B9 A9 C10 B10 C11 B11 C12 C13 B13 A13 D12 E12 D11 E11 D10 E10 D9 E9 D8 E8 C5 B5 A5 C6 B6 A6 C7 B7 A18 B17 A17 C16 B16 A16 C15 B15 13 netX100/500 Host Interface netX100/500 parts that have to be connected to power supply, but are unused 4 ADU0 ADU1 A 1 14 Page of Page 14 5 3 J I H G F E D C B A netX100/500 Quick Start 20/158 Figure 18: netX100/500 Basic Circuit ADC, Host Interface, PHY, RTC © Hilscher, 2008-2012 J I H G F E D C B C404 1 2 2 1 2.2k Date Name Date C402 FB GND VOUT CSH LDS VSW BST 1 C410 2 3 5 4 8 2 24.10.2011 Matthias Melzer 0805 22uF 1 2 4 1 4 C408 S 1 2 1 2 2 1.5k R408 4.7k R407 0603 100nF G 100nF C407 100nF C405 4 6 5 3 2 1 GND PMEG4005 R404 1 PMEG4005 2 5 6 R403 3 4 2 3 1 FB SW 3 FAN2001 PGND AGND EN VIN T402 7 4 6 2 3 G 2 GND S D1 D2 D3 D4 1 1 2 2 4 1 2 5 6 1.96k R412 1.8k R411 2 4 www.hilscher.com 5 GND +3V3 C411 6 GND 2 7 +1V5 2 0805 1 10uF C414 8 6 7 POWER_SUPPLY 8 netX100/500 basic circuit 0805 22uF 1 +1V5 C409 0.018 R406 10uH 4A R405 0805 22uF 1 2 1 2 1 C406 0805 10uF 1 FDC5612 K401 5 Hilscher Gesellschaft für Systemautomatiom mbH 3.3µH IND-LSFS3.3UA1.18 1 R410 Power Supply 1.5V 3 FDC5612 D4 1 2 5 6 0805 K402 D2 D3 11 10 GND 2 0805 1 D1 C403 12 HSD 7 VDD MIC2198 13 9 STEPDOWN-MIC2198YML GND1 2 3 Power Supply 3.3V 1210 10uF 1 6 VIN 2 EN/UVLO T401 COMP 2 1210 10uF 1 +3V3 1 Name R402 0603 2.2nF 1 GND 2 Checked Edited C401 power in line 9V-24V 1210 10uF 1 9V-24V Synchronous Buck Controller A 0603 0603 0603 2 0603 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public 0603 1206 1 2 0603 1 2 0603 1 2 0603 1 2 0603 1 10 11 100nF 9 GND C416 100nF C415 100nF C413 100nF C412 10 +3V3 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 11 Y2 GND AA2 J9 J13 K10 K11 K12 L9 L10 L11 L12 L13 M10 M11 M12 N9 N13 Y1 +3V3 VDDIO_20 AA1 VDDIO_21 Y21 +3V3 VDDIO_18 AA21 VDDIO_19 A21 +3V3 VDDIO_16 B21 VDDIO_17 MICRO-NETX500-2210.000 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 L1 VDDC_17 L2 VDDC_18 GND J10 J11 J12 K9 K13 M9 M13 N10 N11 N12 E17 J19 K21 A2 A20 Y20 AA20 +1V5 +1V5 Y12 VDDC_15 AA12 VDDC_16 +1V5 L20 VDDC_13 L21 VDDC_14 A1 VDDIO_14 B1 VDDIO_15 +1V5 A12 VDDC_11 B12 VDDC_12 D7 +3V3 E7 D15 E15 L17 L18 U15 V15 U7 V7 U6 L4 L5 VDDIO_1 VDDIO_2 VDDIO_3 VDDIO_4 VDDIO_5 VDDIO_6 VDDIO_7 VDDIO_8 VDDIO_9 VDDIO_10 VDDIO_11 VDDIO_12 VDDIO_13 +3V3 A15 VDDH_1 A10 VDDH_2 A8 VDDH_3 +1V5 K17 VDDC_1 K18 VDDC_2 T17 VDDC_3 T18 VDDC_4 U3 VDDC_5 C20 VDDC_6 C21 VDDC_7 D21 VDDC_8 J17 VDDC_9 J18 VDDC_10 K1-N GND 2 0603 1 2 0603 1 2 0603 1 2 0603 1 netX100/500 Power Supply Pins 9 12 100nF C422 100nF C420 100nF C419 100nF C417 12 1 2 0805 1 2 0805 10uF C421 10uF C418 13 +3V3 13 14 Page of Page 14 5 4 J I H G F E D C B A netX100/500 Quick Start 21/158 Figure 19: netX100/500 Basic Circuit Power Supply © Hilscher, 2008-2012 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public J I H G F E D C B A 1 Checked Edited 1 Date Name Date Name 2 24.10.2011 Matthias Melzer 2 3 3 8 unused parts of netX100/500 7 10 PIO8 PIO9 PIO10 PIO11 PIO12 PIO13 PIO14 PIO15 PIO16 PIO17 PIO18 PIO19 PIO20 PIO21 PIO22 PIO23 PIO24 PIO25 PIO26 PIO27 PIO28 PIO29 PIO30 W12 V12 U12 AA11 Y11 W11 V11 U11 AA10 Y10 W10 V10 U10 AA9 Y9 W9 V9 U9 AA8 Y8 W8 V8 U8 M21 M20 M19 M18 M17 N17 P17 R17 4 www.hilscher.com 5 Hilscher Gesellschaft für Systemautomatiom mbH MICRO-NETX500-2210.000 K1-G MICRO-NETX500-2210.000 PIO0 PIO1 PIO2 PIO3 PIO4 PIO5 PIO6 PIO7 6 7 8 UNUSED_NETX-PARTS 9 V20 T20 V21 T21 U20 XM3_TX U21 XM3_RX U19 XM3_IO0 U18 XM3_IO1 R20 XM2_TX R21 XM2_RX R19 XM2_IO0 R18 XM2_IO1 P20 XM1_TX P21 XM1_RX P19 XM1_IO0 P18 XM1_IO1 N20 XM0_TX N21 XM0_RX N19 XM0_IO0 N18 XM0_IO1 10 MICRO-NETX500-2210.000 XC3 XM3_ECLK XC2 XM2_ECLK XC1 XM1_ECLK XC0 XM0_ECLK K1-C Fieldbus Interface MICRO-NETX500-2210.000 JT_TDI JT_TDO JT_TMS JT_TCLK JT_TRST K1-M V14 U14 U16 U13 U17 9 K1-B netX100/500 basic circuit 6 JTAG 5 PIO-Pins 1-30 4 11 11 12 12 13 13 14 Page of Page 14 5 5 J I H G F E D C B A netX100/500 Quick Start 22/158 Figure 20: netX100/500 Basic Circuit Unused netX Parts © Hilscher, 2008-2012 netX100/500 Quick Start 23/158 Bill of Materials Page 1 REF DES PART Type PART NAME C101 EEPROM AT88SC0104CA-SU C102 Ceramic Capacitor 100 nF 25 V 0603 C103 Flash Memory AT45DB321D-SU C104 Ceramic Capacitor 100 nF 25 V 0603 C105 Ceramic Capacitor 100 nF 25 V 0603 C106 Ceramic Capacitor 22 pF 50 V 0603 C107 Ceramic Capacitor 22 pF 50 V 0603 C108 Ceramic Capacitor 1 nF 50 V 0603 G101 Crystal ABM7-25.000 MHZ-D2Y-T K1 Microcontroller netX100/500 P101 LED HSMF-C156 Q101 Reset MAX809SEUR-T R101 Resistor 15 kΩ 63 mW 0603 R102 Resistor 15 kΩ 63 mW 0603 R103 Resistor 1.27 kΩ 63 mW 0603 R104 Resistor 1.27 kΩ 63 mW 0603 R105 Resistor 220 Ω 63 mW 0603 R106 Resistor 220 Ω 63 mW 0603 R107 Resistor 10 kΩ 63 mW 0603 R108 Resistor 10 kΩ 63 mW 0603 R109 Resistor 10 kΩ 63 mW 0603 R110 Resistor 10 kΩ 63 mW 0603 R111 Resistor 1.5 kΩ 63 mW 0603 R112 Diode SN65220DBVT R114 Resistor 24 Ω 63 mW 0603 R115 Resistor 24 Ω 63 mW 0603 X101 USB-B KUSB-BS-1-N-BLK X102 Pin Header 2 pin X103 Pin Header 2 pin Table 1: BOM Basic Circuit Page 1 Page 2 REF DES PART Type PART NAME C201 SDRAM IS42S32200C1-7TLI C202 Ceramic Capacitor 100 nF 25 V 0603 C203 Ceramic Capacitor 100 nF 25 V 0603 C204 Ceramic Capacitor 100 nF 25 V 0603 C205 Ceramic Capacitor 100 nF 25 V 0603 Table 2: BOM Basic Circuit Page 2 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX100/500 Quick Start 24/158 Page 3 REF DES PART Type PART NAME C301 Ceramic Capacitor 100 nF 25 V 0603 C302 Ceramic Capacitor 100 nF 25 V 0603 R301 Resistor 12.4 kΩ 63 mW 0603 R302 Resistor 10 kΩ 63 mW 0603 Table 3: BOM Basic Circuit Page 3 Page 4 REF DES PART Type PART NAME C401 Ceramic Capacitor 10 µF 50 V 1210 C402 Ceramic Capacitor 10 µF 50 V 1210 C403 Ceramic Capacitor 10 µF 50 V 1210 C404 Ceramic Capacitor 2.2nF 50 V 0603 C405 Ceramic Capacitor 100 nF 50 V 0805 C406 Ceramic Capacitor 10 µF 10 V 0805 C407 Ceramic Capacitor 100 nF 50 V 0805 C408 Ceramic Capacitor 100 nF 25 V 0603 C409 Ceramic Capacitor 22 µF 6.3 V 0805 C410 Ceramic Capacitor 22 µF 6.3 V 0805 C411 Ceramic Capacitor 22 µF 6.3 V 0805 C412 Ceramic Capacitor 100 nF 25 V 0603 C413 Ceramic Capacitor 100 nF 25 V 0603 C414 Ceramic Capacitor 10 µF 10 V 0805 C415 Ceramic Capacitor 100 nF 25 V 0603 C416 Ceramic Capacitor 100 nF 25 V 0603 C417 Ceramic Capacitor 100 nF 25 V 0603 C418 Ceramic Capacitor 10 µF 10 V 0805 C419 Ceramic Capacitor 100 nF 25 V 0603 C420 Ceramic Capacitor 100 nF 25 V 0603 C421 Ceramic Capacitor 10 µF 10 V 0805 C422 Ceramic Capacitor 100 nF 25 V 0603 K401 Transistor FDC5612 K402 Transistor FDC5612 R402 Resistor 2.2 kΩ 63 mW 0603 R403 Diode DIODE-SCHOTTKY-PMEG4005AEV R404 Diode DIODE-SCHOTTKY-PMEG4005AEV R405 Inductor CDRH8D43NP-100N R406 Resistor 0.018 Ω 250mW 1206 R407 Resistor 4.7 kΩ 63 mW 0603 R408 Resistor 1.5 kΩ 63 mW 0603 R410 Inductor CR32NP-3R3M R411 Resistor 1.8 kΩ 63 mW 0603 R412 Resistor 1.96 kΩ 63 mW 0603 T401 Step-Down MIC2198YML T402 Step-Down FAN2001MPX Table 4: BOM Basic Circuit Page 4 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public J I H G F E D C B A 1 Checked Edited V20 T20 V21 T21 G19 PHY_EXTRES G17 PHY_ATP U20 XM3_TX U21 XM3_RX U19 XM3_IO0 U18 XM3_IO1 R20 XM2_TX R21 XM2_RX R19 XM2_IO0 R18 XM2_IO1 P20 XM1_TX P21 XM1_RX P19 XM1_IO0 P18 XM1_IO1 Date Name Date Name 2 03.11.2011 Matthias Melzer MICRO-NETX500-2210.000 XC3 XM3_ECLK XC2 XM2_ECLK XC1 XM1_ECLK N20 XM0_TX N21 XM0_RX N19 XM0_IO0 N18 XM0_IO1 GND E21 PHY1_RXN D19 PHY1_VSSAR E19 PHY1_VSSAT1 F19 PHY1_VSSAT2 PHY1_RXN K101-C XC0 F20 PHY1_TYP D20 F21 PHY1_TXN PHY1_TXN E20 PHY1_RXP PHY1_RXP PHY1_TXP PHY1_VDDCART GND H20 PHY0_RXN H18 PHY0_VSSAR H19 PHY0_VSSAT1 G18 PHY0_VSSAR2 PHY0_RXN MICRO-NETX500-2210.000 XM0_ECLK G21 PHY0_TXP H17 GND G20 PHY0_TXN PHY0_TXN H21 PHY0_RXP PHY0_RXP PHY0_TXP PHY0_VDDCART J21 PHY_VSSAT E18 PHY_VSSACP 1 C101 0603 2 0603 100nF 3 12.4k R1092 1 F17 +1V5_FILTERED PHY_VDDCAP J20 +3V3_FILTERED PHY_VDDIOAT F18 PHY_VDDIOAC K101-E netX100/500 3 C102 C104 1 2 GND C105 50 7 R104-B 2 50 R103-B 4 www.hilscher.com 5 6 1 2 0603 1 2 2 0603 1 2 R102 10nF C108 10 R107 +3V3_FILTERED 10nF C106 10 GND 50 6 R104-C GND 50 5 R104-D 50 R103-D 4 5 4 50 8 R103-C +1V5 +3V3 3 6 3 R105 +3V3_FILTERED 1 2 1206 Z=600 Ohm @100MHz +1V5_FILTERED 1 2 R101 1 1206 Z=600 Ohm @100MHz +3V3_FILTERED 7 1 1 2 0603 1 2 2 0603 1 2 10nF C109 10 R108 10nF C107 10 R106 9 6 7 TWISTED_PAIR ETHERNET 8 9 Separeted analog area. Don't place any digital signal in that area. 50 8 R104-A GND 7 2 50 2 1 8 1 0805 10uF R103-A GND 0603 100nF 1 5 Hilscher Gesellschaft für Systemautomatiom mbH GND 2 0805 10uF 1 4 X4 X4 2 X4 X4 X4 X4 0603 0603 X4 X4 10 10 11 11 27 PE1 28 PE2 29 PE3 X101-E RXN0 TXN0 RXP0 TXP0 6 4 5 7 8 2 3 1 RXN1 TXN1 RXP1 TXP1 270 13 270 X4 R110-D 5 2311A 4 AA_YELLOW 12A 24 CA_YELLOW X4 R110-C 3 6 21 9A AA_GREEN 12 6 4 5 7 8 2 3 1 +3V3 +3V3 14 14 Page of Page Ethernet 1 X101-B X101-D X4 270 Ethernet 0 10A 22 CA_GREEN PE 7A 19 8A 20 PHY1_TYP 1A 13 4A 16 PHY1_TXN2A 14 PHY1_RXP 3A 15 5A 17 PHY1_RXN6A 18 PE 1 4 2 3 5 6 7A 7 8A 8 PHY0_TXP 1A 4A PHY0_TXN2A PHY0_RXP 3A 5A PHY0_RXN6A 1111A AA_YELLOW 12A 12 CA_YELLOW X4 R110-B 2 7 270 R110-A 1 8 13 X101-A 9 9A AA_GREEN 10A 10 CA_GREEN X101-C 12 1 1 J I H G F E D C B A 2.2.1 0603 2.2 0603 1 netX100/500 Quick Start 25/158 Ethernet Interface Circuits Twisted Pair Two Channel Figure 21: Ethernet TP Dual Channel Circuit © Hilscher, 2008-2012 netX100/500 Quick Start 26/158 Bill of Materials REF DES PART NAME PART NAME C101 Ceramic Capacitor 100 nF 25 V 0603 C102 Ceramic Capacitor 10 µF 10 V 0805 C104 Ceramic Capacitor 100 nF 25 V 0603 C105 Ceramic Capacitor 10 µF 10 V 0805 C106 Ceramic Capacitor 10 nF 50 V 0603 C107 Ceramic Capacitor 10 nF 50 V 0603 C108 Ceramic Capacitor 10 nF 50 V 0603 C109 Ceramic Capacitor 10 nF 50 V 0603 K101 Microcontroller netX100/500 R101 Ferrite 100 MHz 600 Ω 1 A 1206 R102 Ferrite 100 MHz 600 Ω 1 A 1206 R103 Resistor Array 4x 50 Ω 62 mW 1206 R104 Resistor Array 4x 50 Ω 62 mW 1206 R105 Resistor 10 Ω 63 mW 0603 R106 Resistor 10 Ω 63 mW 0603 R107 Resistor 10 Ω 63 mW 0603 R108 Resistor 10 Ω 63 mW 0603 R109 Resistor 12.4 kΩ 63 mW 0603 R110 Resistor Array 4x 270 Ω 62 mW 1206 X101 RJ45 ERNI-203313 Table 5: BOM Ethernet TP Two Channel More about Ethernet circuits can be found on: Æ Page 102 chapter 4.10 Ethernet Interface netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public J I H G F E D C B 1 Checked Edited V20 T20 V21 T21 G19 PHY_EXTRES G17 PHY_ATP U20 XM3_TX U21 XM3_RX U19 XM3_IO0 U18 XM3_IO1 R20 XM2_TX R21 XM2_RX R19 XM2_IO0 R18 XM2_IO1 P20 XM1_TX P21 XM1_RX P19 XM1_IO0 P18 XM1_IO1 N20 XM0_TX N21 XM0_RX N19 XM0_IO0 N18 XM0_IO1 Date Name Date Name 2 03.11.2011 Matthias Melzer MICRO-NETX500-2210.000 XC3 XM3_ECLK XC2 XM2_ECLK XC1 XM1_ECLK E21 D19 PHY1_VSSAR E19 PHY1_VSSAT1 F19 PHY1_VSSAT2 PHY1_RXN K101-C XC0 F20 D20 F21 PHY1_TXN E20 PHY1_RXP PHY1_TXP PHY1_VDDCART GND H20 PHY0_RXN H18 PHY0_VSSAR H19 PHY0_VSSAT1 G18 PHY0_VSSAR2 PHY0_RXN MICRO-NETX500-2210.000 XM0_ECLK G21 PHY0_TXP H17 GND G20 PHY0_TXN PHY0_TXN H21 PHY0_RXP PHY0_RXP PHY0_TXP PHY0_VDDCART J21 PHY_VSSAT E18 PHY_VSSACP 1 C101 0603 2 0603 100nF 3 12.4k R1092 1 F17 +1V5_FILTERED PHY_VDDCAP J20 +3V3_FILTERED PHY_VDDIOAT F18 PHY_VDDIOAC K101-E netX100/500 1 C102 1 C104 8 GND 50 2 R103-A GND 1 C105 4 www.hilscher.com 5 2 0603 1 2 +3V3_FILTERED R105 10nF C106 10 R102 GND 50 6 R103-C +1V5 +3V3 3 1 2 1206 Z=600 Ohm @100MHz +1V5_FILTERED 1 R101 1 2 1206 Z=600 Ohm @100MHz +3V3_FILTERED 7 50 5 R103-D 4 8 1 2 0603 1 2 10nF C107 10 R106 9 6 7 TWISTED_PAIR ETHERNET 8 9 Separeted analog area. Don't place any digital signal in that area. 50 7 R103-B 6 2 0805 10uF 1 2 0603 100nF Hilscher Gesellschaft für Systemautomatiom mbH GND 2 0805 10uF X4 A 5 X4 4 0603 3 X4 2 X4 10 10 11 11 6 4 5 7 8 2 3 1 15 PE1 16 PE2 MODULAR-JACKS-ERNI-203199 11 AY AA_YELLOW CY 12 CA_YELLOW MODULAR-JACKS-ERNI-203199 9 AG AA_GREEN X101-B RXN0 TXN0 RXP0 TXP0 13 270 0603 R1112 1 270 0603 R1102 1 +3V3 14 14 Page of Page Ethernet 0 MODULAR-JACKS-ERNI-203199 X110-C 12 13 X101-A CG 10 CA_GREEN PE 1 4 2 3 5 6 P7 7 P8 8 PHY0_TXP P1 P4 PHY0_TXNP2 PHY0_RXP P3 P5 PHY0_RXNP6 12 1 1 J I H G F E D C B A 2.2.2 0603 1 netX100/500 Quick Start 27/158 Twisted Pair Single Channel The following figure shows the netX100/500 Ethernet circuit with only on channel. Figure 22: Ethernet TP Single Channel Circuit © Hilscher, 2008-2012 netX100/500 Quick Start 28/158 Bill of Materials REF DES PART TYPE PART NAME C101 ceramic capacitor 100 nF 25 V 0603 C102 ceramic capacitor 10 µF 10 V 0805 C104 ceramic capacitor 100 nF 25 V 0603 C105 ceramic capacitor 10 µF 10 V 0805 C106 ceramic capacitor 10 nF 50 V 0603 C107 ceramic capacitor 10 nF 50 V 0603 K101 Microcontroller netX100/500 R101 Ferrite 100 MHz 600 Ω 1 A 1206 R102 Ferrite 100 MHz 600 Ω 1 A 1206 R103 Resistor Array 4x 50 Ω 62 mW 1206 R105 Resistor 10 Ω 63 mW 0603 R106 Resistor 10 Ω 63 mW 0603 R109 Resistor 12.4 kΩ 63 mW 0603 R110 Resistor 270 Ω 63 mW 0603 R111 Resistor 270 Ω 63 mW 0603 X101 RJ45 ERNI-203199 Table 6: BOM Ethernet TP Single Channel More about SDRAM circuits can be found on: Æ Page 102 chapter 4.10 Ethernet Interface netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 J I H G F E D C B A 1 checking draw I2C_SDA E21 PIO0 PIO1 PIO2 PIO3 PIO4 PIO5 PIO6 PIO7 1 4 2 0603 1 2 0805 10uF 1 5 T21 +1V5 +3V3 4 6 2 GND +3V3 8 1 2 10k R410 Regard thermal considerations (see datasheet) 1 place close to netX 9 1 2 2 100nF 100nF 6 ETH1_SD 47k R414 +3V3 R411 +3V3 7 6 7 8 9 5 C407 ETH1_RX 2 0603 1 8 6 +3V3 7 ETH0_RX 5 C406 ETH0_SD 2 0603 1 100nF ETH1_TX 8 6 +3V3 7 5 C405 8 ETH0_TX 2 10k GND GND GND 0603 1 +3V3 10 10 ETHERNET_FIBER_OPTIC_INTERFACE_1 netX100/500 MAX4643EUA GND COM2 5 NC2 3 IN2 VCC 8 U20 XM3_TX U21 XM3_RX U19 XM3_IO0 U18 XM3_IO1 R20 XM2_TX R21 XM2_RX R19 XM2_IO0 R18 XM2_IO1 P20 ETH1_TX XM1_TX P21 ETH1_RX XM1_RX P19 ETH1_SD XM1_IO0 P18 TX1_DISABLE_INV XM1_IO1 I2C_SDA I2C_SDA_SW K402 7 N20 ETH0_TX XM0_TX N21 ETH0_RX XM0_RX N19 ETH0_SD XM0_IO0 N18 TX0_DISABLE_INV XM0_IO1 MICRO-NETX500-2210.000 XC3 XM3_ECLK XC2 XM2_ECLK XC1 XM1_ECLK XC0 XM0_ECLK K101-C 1 2 1206 Z=600 Ohm @100MHz COM1 V20 T20 V21 100nF C404 1 NO1 7 IN1 2 0603 R402 1 R401 2 1206 Z=600 Ohm @100MHz 6 I2C_SDA I2C_SDA_SW C403 Hilscher GmbH 100nF C402 65795 Hattersheim 2 10uF C401 Date GND 2 5 Rheinstrasse 15 3 I2C_SDA_SW 1 0805 4 Name 17.10.2012 12.4k 0603 R4032 1 FX0_COM-G FX0_COM-R FX1_COM-G FX1_COM-R Matthias Melzer M21 M20 M19 M18 M17 N17 P17 R17 G19 PHY_EXTRES G17 PHY_ATP D19 PHY1_VSSAR E19 PHY1_VSSAT1 F19 PHY1_VSSAT2 PHY1_RXN MICRO-NETX500-2210.000 Date F20 D20 F21 PHY1_TXN E20 PHY1_RXP PHY1_TXP PHY1_VDDCART K101-B Name H20 H18 PHY0_VSSAR H19 PHY0_VSSAT1 G18 PHY0_VSSAR2 PHY0_RXN MICRO-NETX500-2210.000 [1] G21 G20 PHY0_TXN H21 PHY0_RXP PHY0_TXP PHY0_VDDCART H17 J21 PHY_VSSAT E18 PHY_VSSACP PHY_VDDCAP F17 J20 PHY_VDDIOAT F18 PHY_VDDIOAC K101-E 3 0603 2 0603 0603 1 Q1 Q0 1 2 2 11 47k R415 10k 11 SY89323LMGTR K405 SY89323LMGTR K404 SY89322VMGTR K403 R412 GND VCC Q1 Q0 GND VCC IN1 IN0 GND VCC 0603 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public 1 IN1 IN1# IN0 IN0# IN1 IN1# IN0 IN0# Q1 Q1# Q0 Q0# 2 0603 10k R413 4 3 1 2 4 3 1 2 3 4 1 2 12 GND TX1_DISABLE_INV GND TX0_DISABLE_INV 12 1 1 2 GND 2 130 R405 82 R404 +3V3 NC7SZ14P5 13 5 VCC Y 4 K407 NC7SZ14P5 2 A 3 GND 13 5 VCC Y 4 K406 2 A 3 GND 0603 0603 +3V3 +3V3 14 Page of I2C_SDA0 I2C_SDA1 FX0_COM-G FX0_COM-R FX1_COM-G FX1_COM-R Page [5] [5] [5] [5] [5] [5] [5] FX1_SD-P [5] FX1_RX+ [5] FX1_RX- [5] FX0_SD-P [5] FX0_RX+ [5] FX0_RX- [5] FX1_TX+ [5] FX1_TX- [5] FX0_TX+ [5] FX0_TX- 6 4 [5] FX1_TX-DISABLE [5] FX0_TX-DISABLE 14 J I H G F E D C B A 2.2.3 0603 1 netX100/500 Quick Start 29/158 Fiber Optic with AFBR-5978Z The first figure shows the connection on the netX100/500 side. Figure 23: Fiber Optic Circuit on netX100/500 Side © Hilscher, 2008-2012 J I H G F E D C B A [4] [4] [4] [4] [4] [4] FX1_TX+ FX1_TXFX1_TX-DISABLE FX1_RX+ FX1_RXFX1_SD-P 1 1 green 1 green 4 5 1 1 2 1 2 1 2 2 82 R518 130 R515 82 R504 130 R501 1 1 2 1 1 2 1 8 1 2 1 GND 2 1 2 GND 2 82 R520 130 R517 82 R506 130 R503 9 1 1 2 2 195 R521 195 R507 1 1 2 2 6 7 8 9 2 0805 1 2 0805 1 10uF C506 10uF C501 11 GND 2 0603 1 +3V3 GND 2 0603 1 +3V3 100nF C507 100nF C502 2 10uF 1μH 2 1μH 2 1 10uF 2 2 X501 100nF X502 100nF C509 AFBR-5978Z 6 RDATA+ 5 RDATA4 SD 10 TDATA+ 11 TDATA9 TXDIS 1 SDA 12 SCL 2 0603 AFBR-5978Z 6 RDATA+ 5 RDATA4 SD 1 13 C504 10 TDATA+ 11 TDATA9 TXDIS C508 1μH 1 0603 1 SDA 12 SCL C503 R424 1 0805 1 2 2 R423 1 0805 1 1μH R510 1 R509 12 7 GND 1 GND 2 0603 1 GND 2 0603 100nF C510 100nF C505 14 10 11 12 13 14 Page of Page Note: FX0 / 1 Link and ACT LED can be connected to any free PIO. The PIOs can be configured in the netX Tag List Editor. 195 R522 195 R508 place close to X401, X402 10 ETHERNET_FIBER_OPTIC_INTERFACE_2 2 82 R519 130 R516 +3V3 2 82 R505 130 R502 +3V3 place close to K103, K104, K105 7 netX100/500 FX1 ACT LED FX1 LINK LED +3V3 FX1 COM1 LED +3V3 Hilscher GmbH 3 yellow LEDSYG 4 2 P504 3 red LEDSRG 4 2 P503 FX0 ACT LED FX0 LINK LED +3V3 65795 Hattersheim 3 1 green 3 yellow LEDSYG 4 2 P502 6 FX0 COM0 LED +3V3 5 Date 2 270 0603 green 3 red 1 LEDSRG 4 2 P501 4 Rheinstrasse 15 17.10.2012 Matthias Melzer 270 0603 R5282 1 1 R5272 470 0603 R5262 1 270 0603 270 0603 R5252 1 1 R5142 270 0603 470 0603 R5132 1 1 R5122 270 0603 R5112 1 3 Name Date Name FX1_ACT FX1_LNK FX1_COM-R [4] FX1_COM-G [4] [4] [1,5] FX0_ACT FX0_LNK FX0_COM-R [4] FX0_COM-G [4] I2C_SDA1 I2C_SCL checking draw [4] [4] [4] [4] [1,5] FX0_RX+ [4] FX0_RX- [4] FX0_SD-P [4] FX0_TX+ FX0_TXFX0_TX-DISABLE I2C_SDA0 I2C_SCL 2 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 3 RXVCC RXGND 2 TXVCC TXGND 8 7 RXVCC 3 TXVCC TXGND RXGND 8 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public 2 1 6 5 J I H G F E D C B A netX100/500 Quick Start 30/158 The second figure shows the circuit on the AFBR-5978Z side. Important is to place the level transistors close to netX100/500 and AC-termination (R501 – R510 and R17 – R526) close to the level transistors. Figure 24: Fiber Optic Circuit on AFBR-5978Z Side © Hilscher, 2008-2012 netX100/500 Quick Start 31/158 Bill of Materials Page 1 REF DES PART TYPE PART NAME C401 Ceramic Capacitor 10 µF 10 V 0805 C402 Ceramic Capacitor 100 nF 25 V 0603 C403 Ceramic Capacitor 10 µF 10 V 0805 C404 Ceramic Capacitor 100 nF 25 V 0603 C405 Ceramic Capacitor 100 nF 25 V 0603 C406 Ceramic Capacitor 100 nF 25 V 0603 C407 Ceramic Capacitor 100 nF 25 V 0603 K101 Microcontroller netX100/500 K402 IC-Switch MAX4643EUA K403 Driver SY89322VMGTR K404 Driver SY89323LMGTR K405 Driver SY89323LMGTR K406 Schmitt Trigger and Inverter NC7SZ14P5X K407 Schmitt Trigger and Inverter NC7SZ14P5X R401 Ferrite 100 MHz 600 Ω 1 A 1206 R402 Ferrite 100 MHz 600 Ω 1 A 1206 R403 Resistor 12.4 kΩ 63 mW 0603 R404 Resistor 82 Ω 63 mW 0603 R405 Resistor 130 Ω 63 mW 0603 R410 Resistor 10 kΩ 63 mW 0603 R411 Resistor 10 kΩ 63 mW 0603 R412 Resistor 10 kΩ 63 mW 0603 R413 Resistor 10 kΩ 63 mW 0603 R414 Resistor 47 kΩ 63 mW 0603 R415 Resistor 47 kΩ 63 mW 0603 Table 7: BOM Fiber Optic Page 1 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX100/500 Quick Start 32/158 Page 2 REF DES PART TYPE PART NAME C501 Ceramic Capacitor 10 µF 10 V 0805 C502 Ceramic Capacitor 100 nF 25 V 0603 C503 Ceramic Capacitor 10 µF 10 V 0805 C504 Ceramic Capacitor 100 nF 25 V 0603 C505 Ceramic Capacitor 100 nF 25 V 0603 C506 Ceramic Capacitor 10 µF 10 V 0805 C507 Ceramic Capacitor 100 nF 25 V 0603 C508 Ceramic Capacitor 10 µF 10 V 0805 C509 Ceramic Capacitor 100 nF 25 V 0603 C510 Ceramic Capacitor 100 nF 25 V 0603 P501 LED HSMF-C155 1210 P503 LED HSMF-C155 1210 R501 Resistor 130 Ω 63 mW 0603 R502 Resistor 130 Ω 63 mW 0603 R503 Resistor 130 Ω 63 mW 0603 R506 Resistor 82 Ω 63 mW 0603 R507 Resistor 82 Ω 63 mW 0603 R508 Resistor 82 Ω 63 mW 0603 R509 Resistor 82 Ω 63 mW 0603 R510 Resistor 82 Ω 63 mW 0603 R511 Ferrite 1 µH 0,28 Ω 600mA 1812 R512 Ferrite 1 µH 0,28 Ω 600mA 1812 R513 Resistor 270 Ω 63 mW 0603 R514 Resistor 470 Ω 63 mW 0603 R517 Resistor 130 Ω 63 mW 0603 R518 Resistor 130 Ω 63 mW 0603 R519 Resistor 130 Ω 63 mW 0603 R522 Resistor 82 Ω 63 mW 0603 R523 Resistor 82 Ω 63 mW 0603 R524 Resistor 82 Ω 63 mW 0603 R525 Resistor 82 Ω 63 mW 0603 R526 Resistor 82 Ω 63 mW 0603 R527 Ferrite 1 µH 0,28 Ω 600mA 1812 R528 Ferrite 1 µH 0,28 Ω 600mA 1812 R529 Resistor 270 Ω 63 mW 0603 R530 Resistor 470 Ω 63 mW 0603 X501 Fiber Optic Connector AFBR-5978Z X502 Fiber Optic Connector AFBR-5978Z Table 8: BOM Fiber Optic Page 2 More about SDRAM circuits can be found on: Æ Page 105 chapter 4.10.2 Fiber Optic netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public J I H G F E D C B Edited 1 PIO5 PIO4 XM2_TX XM2_IO0 XM2_RX Date 2 06.10.2011 VDD2 green 1210 3 +1V5 ADUM1301CRW ISOLATOR-ADUM1301CRW VIC VIB 4 3 2 1 2 100k R103 4 5 Reinstraße 15 65795 Hattersheim www.hilscher.com Hilscher GmbH 7 VE1 5 VOC 13 VOB 10 VE2 12 1 2 GND1-1 8 GND1-2 VDD1 VIA K101 VOA 14 9 GND2-1 15 GND2-2 16 3 red 1 LEDSRG 4 2 P101 Matthias Melzer 470 0603 R1022 1 270 0603 R1012 1 2 GND Name C101 0603 100nF 1 +1V5 C102 0805 10uF 1 ISOLATED-AREA 5 0603 A 4 C103 2 1 1 2 2 ISOTX1 ISORX1 10k R105 0603 10k 6 7 VOUTC1 2 8 8 C105 Tantal 22uF 1 V5AC1 R1061 2 C104 0805 100nF 1 7 AS-INTERFACE 2 10k R104 0603 100nF 1 6 0603 3 0603 2 22 21 16 15 14 13 5 4 24 K102 9 UIN 2 1 6 7 28 25 CAP 3 0V 12 GND ASIN ASIP OSC2 OSC1 ASI4CU-E-M DRIVER-ASI4CU-E-M DSR PST P0 P1 P2 P3 FID TXD/IRD RXD/LED 11 DO0 10 DO1 9 DO2 8 DO3 17 DI0 18 DI1 19 DI2 20 DI3 23 U5RD 26 U5R 27 UOUT VOUTC1 9 8MHz 10 ASI-C_1 ASI+IN_1 10 3 1 4.7mH 2 11 SOD 80 2 LL4148L 1 R108 RS-CM7050-8 G101 1 R107 11 2 1 1 2 R109 R110 1 1 2 1 2 1 2 12.4k 2 13 1 2 ASI+ ASI- X101 14 1 Page of 14 1 Page ASI4U: Ref.-Spg = 2.0V C106 0603 10nF 1 R40 = 4.02k ASI4U: R40 = 8.2k R114 12 2 1k R113A2SI: R40 = 10k ASI4U: R40 = 33k R112A2SI: 22k 1 4 0.470mH 2 3 R115 13 ASi-Powerfail = 22.5V (+/-1V) LL4148L R111 1N4004-SMD BZG03C39 ASI+IN1 12 SOD 80 0603 0603 J I H G F E D C B A 2.3 0603 1 netX100/500 Quick Start 33/158 AS-Interface Figure 25: AS-Interface Circuit © Hilscher, 2008-2012 netX100/500 Quick Start 34/158 Bill of Materials REF DES PART TYPE PART NAME C101 Ceramic Capacitor 100 nF 25 V 0603 C102 Ceramic Capacitor 10 µF 10 V 0805 C103 Ceramic Capacitor 100 nF 25 V 0603 C104 Ceramic Capacitor 100 nF 50 V 0805 C105 Tantalum Capacitor 22 µF 35 V C106 Ceramic Capacitor 10 nF 50 V 0603 G101 Crystal RS-CM7050 8 MHz K101 Triple-Channel Digital Isolators ADUM1301CRW K102 Advanced AS-Interface IC ASI4UC-E-M P101 LED red/green HSMF-C155 R101 Resistor 270 Ω 63 mW 0603 R102 Resistor 470 Ω 63 mW 0603 R103 Resistor 100 kΩ 63 mW 0603 R104 Resistor 10 kΩ 63 mW 0603 R105 Resistor 10 kΩ 63 mW 0603 R106 Resistor 10 kΩ 63 mW 0603 R107 Inductor 4.7 mH 0.1 A Würth Elektronik Part No. 744775347 R108 Diode LL4148L R109 Diode SM4004 R110 Diode BZG03C39 R111 Diode LL4148L R112 Resistor 22 kΩ 63 mW 0603 R113 Resistor 1 kΩ 63 mW 0603 R114 Resistor 12.4 kΩ 63 mW 0603 R115 Inductor EPCOS B82790C0474N215 X101 Connector MC1,5/2-G-3,81 Table 9: BOM AS-Interface Circuit More about AS-Interface circuits can be found on: Æ Page 118 chapter 4.11 Fieldbus Interface Æ Page 120 chapter 4.11.1 AS interface Master Æ Page 126 chapter 4.11.7 Fieldbus Status LEDs netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public J I H G F E D C B Edited 1 PIO5 PIO4 Date Name +3V3 XM2_RX XM2_TX 1 2 10.10.2011 Matthias Melzer 1 270 470 0603 3 C105 green 1210 6 7 5 8 3 2 1 2 +3V3 VO VE GND VCC CAT ANO 5V DC 0 OUT PSD-3R305S 0 IN + 3,3V DC + T101 HCPL060L & K102 HCPL0601 & K101 4 5 CAT ANO VO VE GND VCC 3 2 6 7 5 8 4 www.hilscher.com 5 C101 2 C106 6 CAN 0805 22uF 1 470 0603 R1042 1 ISOGND_CAN ISO+5V_CAN 2 0603 100nF 1 ISO+5V_CAN ISOLATED-AREA 6 1 3 VIN 7 EN 2 5 8 8 ISOGND_CAN 470 R102 NCP500SN50T1 VOUT GND 2 1 ISO+5V_CAN T102 7 2 2 7 CANH 6 CANL GND VCC 3 9 ISOGND_CAN ISO+5V_CAN PCA82C251T C107 0805 22uF 1 1 TXD 4 RXD 5 V_REF 8 RS K103 9 C103 10 ISOGND_CAN 2 0603 100nF 1 ISO+5V_CAN 10 11 2 1 11 ISOGND_CAN 3 5 Hilscher Gesellschaft für Systemautomatiom mbH 3 red LEDSRG DIODE-LED-LEDSRG-1210 1 P101 4 2 0805 22uF 1 4 C102 0603 100nF 1 2 GND R1102 2 270 R101 2 0603 1 +3V3 R1092 1 1 2 0805 Z=1000 Ohm @100MHz R108 1 2 0805 Z=1000 Ohm @100MHz R107 2 470 R103 +3V3 3 0603 A 2 0603 0603 1 PESD1CAN R105 2 1M 12 R106 12 2 13 PE C104 1808 15nF 1 X101 CAN-L 14 1 Page of 14 1 Page 1 1 2 2 3 3 4 4 5 5 6 ISOGND_CAN 6 7 CAN-H 7 8 8 9 9 10 SHIELD1 11 SHIELD2 XDCP9SW-6MM 13 J I H G F E D C B A 2.4 2010 1 netX100/500 Quick Start 35/158 CANopen Figure 26: CANopen Circuit © Hilscher, 2008-2012 netX100/500 Quick Start 36/158 Bill of Materials REF DES PART TYPE PART NAME C101 Ceramic Capacitor 100 nF 25 V 0603 C102 Ceramic Capacitor 100 nF 25 V 0603 C103 Ceramic Capacitor 100 nF 25 V 0603 C104 Ceramic Capacitor 15 nF 1000 V 1808 C105 Ceramic Capacitor 22 µF 6.3 V 0805 C106 Ceramic Capacitor 22 µF 6.3 V 0805 C107 Ceramic Capacitor 22 µF 6.3 V 0805 K101 Optocoupler HCPL0601 K102 Optocoupler HCPL060L K103 Transceiver PCA82C251T P101 LED red/green HSMF-C155 R101 Resistor 270 Ω 63 mW 0603 R102 Resistor 470 Ω 63 mW 0603 R103 Resistor 470 Ω 63 mW 0603 R104 Resistor 470 Ω 63 mW 0603 R105 ESD protection diode PESD1CAN R106 Resistor 1M Ω 500 mW 2010 R107 Ferrite 100 Ω 100 MHz 1 A Würth Elektronik Part No. 74279207 R108 Ferrite 100 Ω 100 MHz 1 A Würth Elektronik Part No. 74279207 R109 Resistor 270 Ω 63 mW 0603 R110 Resistor 470 Ω 63 mW 0603 T101 DC/DC Step-Up PEAK part no. PSD-3R305S T102 Voltage Regulator NCP500SN50T1 X101 D-Sub9 Male SUYIN USA part no. 070211MR009G200ZU Table 10: BOM CANopen Circuit More about CANopen circuits can be found on: Æ Page 118 chapter 4.11 Fieldbus Interface Æ Page 121 chapter 4.11.2 CANopen Interface Æ Page 126 chapter 4.11.7 Fieldbus Status LEDs netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public J I H G F E D C B 1 Checked Edited PIO5 PIO4 XM2_RX XM2_TX XM2_IO0 Date Name Date Name 270 0603 470 0603 2 17.11.2011 2 1 2 6 5 8 2 4 1 3 2 VO 1 2 GND2 VDD2 VI GND1 VCC CAT ANO 5V DC 0 OUT PSD-3R305S 0 IN + 3,3V DC + T101 ACPL072L OPTO-ACPL072L K103 ACPL072L OPTO-ACPL072L K102 HCPL0601 OPTO-HCPL0601 & K101 4 5 VI GND1 VCC VO GND2 VDD2 VO VE GND VCC 2 4 1 6 5 8 6 7 5 8 C101 ISOGND_CCL C103 ISOGND_CCL C105 2 2 4 www.hilscher.com 5 1 2 1k 1 3 EN VIN 2 7 GND 5 NCP500SN50T1 VOUT T102 ISO+5V_CCL ISOGND_CCL 5 VCC Y 4 NC7SZ14P5 INV-NC7SZ14P5 CC-LINK 6 7 K104 2 A 3 GND R106 ISOGND_CCL C107 0805 22uF 1 ISOGND_CCL 0603 100nF 1 ISO+5V_CCL 2 0603 100nF 1 ISO+5V_CCL 2 0603 100nF 1 ISO+5V_CCL ISOLATED AREA 6 2 3 5 4 2 R 8 2 B A Z Y C108 9 2 ISOGND_CCL 11 12 10 9 9 ISOGND_CCL ISO+5V_CCL B A Z Y 7 GND2 6 GND1 10 1 1 2 47k 10 ISOGND_CCL 2 680 0603 2 R111 680 1 0603 R1102 1 R109 47k R108 ISO+5V_CCL C110 0603 100nF 1 ISO+5V_CCL 14 VCC2 13 VCC1 75ALS181D DRIVER-75ALS181D R RE D DE K105 ISOGND_CCL 0805 22uF 1 RE# D DE 10k 0603 100nF R1072 1 1 C109 8 11 2 1 11 ISOGND_CCL 3 5 Hilscher Gesellschaft für Systemautomatiom mbH +3V3 C106 0805 22uF 1 2 GND 3 C104 0603 100nF 1 +3V3 2 GND green 1210 P101 C102 GND 0603 100nF 1 +3V3 4 3 red LEDSRG DIODE-LED-LEDSRG-1210 R1052 1 R103 1 2 0805 Z=1000 Ohm @100MHz R1042 1 R102 1 2 0805 Z=1000 Ohm @100MHz 220 Matthias Melzer +3V3 0603 R1012 1 4 0603 A 3 0603 2 0603 12 ISOGND_CCL RD6.2Z R112 R113 L1_1 L1_2 1 6 L2_1 L2_2 2 5 L3_1 L3_2 3 4 ZCYS51R5-M3PAT 12 13 2 PE C111 0805 3.3nF 1 13 14 Page of Page 5 4 3 2 1 X101 14 1 1 J I H G F E D C B A 2.5 0603 1 netX100/500 Quick Start 37/158 CC-Link Figure 27: CC-Link Circuit © Hilscher, 2008-2012 netX100/500 Quick Start 38/158 Bill of Material REF DES PART TYPE PART NAME C101 Ceramic Capacitor 100 nF 25 V 0603 C102 Ceramic Capacitor 100 nF 25 V 0603 C103 Ceramic Capacitor 100 nF 25 V 0603 C104 Ceramic Capacitor 100 nF 25 V 0603 C105 Ceramic Capacitor 100 nF 25 V 0603 C106 Ceramic Capacitor 22 µF 6.3 V 0805 C107 Ceramic Capacitor 22 µF 6.3 V 0805 C108 Ceramic Capacitor 22 µF 6.3 V 0805 C109 Ceramic Capacitor 100 nF 25 V 0603 C110 Ceramic Capacitor 100 nF 25 V 0603 C111 Ceramic Capacitor 3.3 nF 63 V 0805 K101 Optocoupler HCPL0601 K102 Optocoupler ACPL-072L K103 Optocoupler ACPL-072L K104 Schmitt Trigger FAIRCHILD Ord. No.:NC7SZ14P5X K105 Transceiver TEXAS INSTRUMENTS Ord. No. SN75ALS181NSR P101 LED red/green HSMF-C155 R101 Resistor 220 Ω 63 mW 0603 R102 Ferrite 100 Ω 100 MHz 1 A Würth Elektronik Part No. 74279207 R103 Ferrite 100 Ω 100 MHz 1 A Würth Elektronik Part No. 74279207 R104 Resistor 270 Ω 63 mW 0603 R105 Resistor 470 Ω 63 mW 0603 R106 Resistor 1 kΩ 63 mW 0603 R107 Resistor 10 kΩ 63 mW 0603 R108 Resistor 47 kΩ 63 mW 0603 R109 Resistor 47 kΩ 63 mW 0603 R110 Resistor 680 Ω 63 mW 0603 R111 Resistor 680 Ω 63 mW 0603 R112 ESD protection diode RD6.2Z R113 Inductor EMC Components Part No. ZCYS51R5-M3PAT T101 DC/DC Step-Up PSD-3R305S T102 Voltage Regulator NCP500SN50T1 X101 Connector MC1,5/5-G-3,81 Table 11: BOM CC-Link Circuit More about CC-Link circuits can be found on: Æ Page 118 chapter 4.11 Fieldbus Interface Æ Page 122 chapter 4.11.3 CC-Link Interface Æ Page 126 chapter 4.11.7 Fieldbus Status LEDs netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public J I H G F E D C B A 1 Checked Edited PIO7 PIO6 PIO5 PIO4 XM2_TX XM2_IO0 XM2_RX Date Name Date Name 2 C101 +3V3 2 18.11.2011 270 470 0603 3 green 1210 3 red 1 A B GND VCC 6 7 5 8 2 1 C105 2 0805 22uF www.hilscher.com 4 C102 GND 0603 100nF 1 +5V 6 2 200 Ohm LEFS300RA500M-0603 1 R104 1 2 200 Ohm LEFS300RA500M-0603 R103 7 10 0603 R1062 1 R110 2 1 1 5 1 2 5V DC 0 OUT 4 5 6 7 COMPONET PSD-3R305S 0 IN + 3,3V DC + T102 1 C103 2 1 C106 GND 2 0805 22uF T103 8 3 VIN EN 2 GND 9 NCP500SN50T1 VOUT 5 R113 RD6.2SB1 RD6.2SB1 2 1 1 R112 R111 1 2 0603 47pF RD6.2SB1 RD6.2SB1 10 0603 10 2 11 150 11 R109 C104 2 C107 GND 2 0805 22uF 1 1 1 0603 47pF 10 +5V R1082 1 10 10 0603 R1072 1 2 9 R1052 1 0603 8 OPTIONAL if there is no 5V power supply in the circuit +3V3 +3V3 AD51/025 DRIVER-AD51/025 D R K102 5 Hilscher Gesellschaft für Systemautomatiom mbH 1 2 0805 Z=1000 Ohm @100MHz R120 LEDSRG 4 R1182 1 2 0603 DI green 1210 P102 R1172 1 470 1 3 red LEDSRG 4 0603 270 4 R101 1k 4 1 RO 2 RE 3 DE P101 GND 2 2 0603 1 R1162 1 2 1 R1152 1 B A 3 NC7SZ08P5 & K101 5 VCC 4 Y 3 GND Matthias Melzer GND 0603 100nF 1 +3V3 2 0603 0603 1 2 8 22 1 4 4 2 2 3 3 1 03-7104 5 R114 5 7 7 6 6 8 T101 13 12 3 BDH 13 1 4 BDL ACM3225-102-2P 2 R119 ISOLATED AREA 12 14 Page of Page BS+ BDH BDL BSXW7D-PB4-R 1 2 3 4 X101 14 1 1 J I H G F E D C B A 2.6 0603 1 netX100/500 Quick Start 39/158 CompoNet Figure 28: CompoNet Circuit © Hilscher, 2008-2012 netX100/500 Quick Start 40/158 Bill of Material REF DES PART TYPE PART NAME C101 Ceramic Capacitor 100 nF 25 V 0603 C102 Ceramic Capacitor 100 nF 25 V 0603 C103 Ceramic Capacitor 47 pF 50 V 0603 C104 Ceramic Capacitor 47 pF 50 V 0603 K101 2-Input AND Gate NC7SZ08P5 K102 Transceiver AD51/025 P101 LED red/green HSMF-C155 P102 LED red/green HSMF-C155 R101 Resistor 1 kΩ 63 mW 0603 R103 Ferrite TDK Part No. MMZ1608B301C R104 Ferrite TDK Part No. MMZ1608B301C R105 Resistor 10 Ω 63 mW 0603 R106 Resistor 10 Ω 63 mW 0603 R107 Resistor 10 Ω 63 mW 0603 R108 Resistor 10 Ω 63 mW 0603 R109 Resistor 150 Ω 63 mW 0603 R110 Diode NEC Type No. RD6.2S Class: B1 R111 Diode NEC Type No. RD6.2S Class: B1 R112 Diode NEC Type No. RD6.2S Class: B1 R113 Diode NEC Type No. RD6.2S Class: B1 R114 Resistor 22 Ω 63 mW 0603 R115 Resistor 270 Ω 63 mW 0603 R116 Resistor 470 Ω 63 mW 0603 R117 Resistor 270 Ω 63 mW 0603 R118 Resistor 470 Ω 63 mW 0603 R119 Inductor TDK Part No. ACM3225-102-2P T101 Transformer OMRON 03-7104 X101 Connector OMRON XW7D-PB4-R Table 12: BOM CompoNet Circuit Optional Bill of Material C105 Ceramic Capacitor CKSS22UV6.3-0805 C106 Ceramic Capacitor 22 µF 6.3 V 0805 C107 Ceramic Capacitor 22 µF 6.3 V 0805 R120 Ferrite 100 Ω 100 MHz 1 A Würth Elektronik Part No. 74279207 T102 DC/DC Step-Up PEAK part no. PSD-3R305S T103 Voltage Regulator NCP500SN50T1 Table 13: Optional BOM CompoNet Circuit More about CompoNet circuits can be found on: Æ Page 118 chapter 4.11 Fieldbus Interface Æ Page 123 chapter 4.11.4 CompoNet Interface netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public J I H G F E D C 1 Checked Edited GND +3V3 Date Name Date Name PIO5 PIO4 XM2_IO0 XM2_RX XM2_TX 1.3k 16.11.2011 270 470 0603 3 1 4.02k C103 GND 2 R103 +3V3 1 green 1210 3 4 6 7 5 8 3 2 1 2 +3V3 EMI COL VO VE GND VCC CAT ANO & K103 HCPL0601 5V DC 0 OUT PSD-3R305S 0 IN + 3,3V DC + T101 TLP281 K104 HCPL060L & 4 www.hilscher.com 5 6 4 5 CAT ANO CAT ANO VO VE GND VCC 2 1 3 2 6 7 5 8 C104 C107 2 4.02k 3 1 R110 1 EN 6 7 2 GND C106 5 C108 8 ISOGND_DN 2 0805 22uF 1 GND 2 3 9 7 CANH 6 CANL ISOGND_DN 4.3k 0805 9 VCC R1112 1 PCA82C251T K105 ISO+5V_DN NCP500SN50T1 VOUT 2 8 1 TXD 4 RXD 5 V_REF 8 RS 0603 100nF 1 ISOGND_DN 470 T102 VIN 2 R108 ISO+5V_DN 7 DEVICENET 2 0805 22uF 1 1 470 0603 R1092 1 ISOGND_DN ISO+5V_DN 2 0603 100nF 1 ISOLATED-AREA K102 5 Hilscher Gesellschaft für Systemautomatiom mbH 3 red LEDSRG DIODE-LED-LEDSRG-1210 4 R1072 1 0603 C101 P101 2 2 1 2 270 R101 0805 22uF 1 1 4 0603 +3V3 0603 0603 100nF 1 2 GND R1062 1 2 0805 Z=1000 Ohm @100MHz R105 Matthias Melzer 2 74LVC1G17GW 2 A 3 GND K101 5 VCC 4 Y R104 100nF C102 2 R102 1 2 0805 Z=1000 Ohm @100MHz GND 2 0603 1 +3V3 1 +3V3 0603 B 3 0603 2 C105 10 ISOGND_DN 0603 100nF 1 ISO+5V_DN 10 2 1 2 1M 11 PESD1CAN 11 R112 R114 ISOGND_DN 1 A 2 0603 3 2010 1 2 2 12 C109 12 1 2 1M R115 ISOGND_DN RVA30VA800-1812 R113 1808 15nF U 1 1812 13 PE 2 C110 14 X101 1 2 3 4 5 14 Page of Page DN-H ISOGND_DN DN-L 1808 15nF 1 13 1 1 J I H G F E D C B A 2.7 2010 1 netX100/500 Quick Start 41/158 DeviceNet Figure 29: DeviceNet Circuit © Hilscher, 2008-2012 netX100/500 Quick Start 42/158 Bill of Materials REF DES PART TYPE PART NAME C101 Ceramic Capacitor 100 nF 25 V 0603 C102 Ceramic Capacitor 100 nF 25 V 0603 C103 Ceramic Capacitor 22 µF 6.3 V 0805 C104 Ceramic Capacitor 100 nF 25 V 0603 C105 Ceramic Capacitor 100 nF 25 V 0603 C106 Ceramic Capacitor 100 nF 25 V 0603 C107 Ceramic Capacitor 22 µF 6.3 V 0805 C108 Ceramic Capacitor 22 µF 6.3 V 0805 C109 Ceramic Capacitor 15 nF 1000 V 1808 C110 Ceramic Capacitor 15 nF 1000 V 1808 K101 Schmitt Trigger NXP Semiconductors part no. 74LVC1G17GW K102 Optocoupler HCPL0601 K103 Optocoupler HCPL060L K104 Photocoupler & Photo-Transistor TLP281 K105 Transceiver PCA82C251T P101 LED red/green HSMF-C155 R101 Resistor 270 Ω 63 mW 0603 R102 Resistor 1.3 kΩ 63 mW 0603 R103 Resistor 4.02 kΩ 63 mW 0603 R104 Ferrite 100 Ω 100 MHz 1 A Würth Elektronik Part No. 74279207 R105 Ferrite 100 Ω 100 MHz 1 A Würth Elektronik Part No. 74279207 R106 Resistor 270 Ω 63 mW 0603 R107 Resistor 470 Ω 63 mW 0603 R108 Resistor 470 Ω 63 mW 0603 R109 Resistor 470 Ω 63 mW 0603 R110 Resistor 4.02 kΩ 63 mW 0603 R111 Resistor 4.3 kΩ 125 mW 0805 R112 ESD protection diode PEAK part no. PSD-3R305S R113 Varistor Epcos Type: SIOV-CN1812K30G Ord. Code: B72580 V0300K062 R114 Resistor 1M Ω 500 mW 2010 R115 Resistor 1M Ω 500 mW 2010 T101 DC/DC Step-Up PEAK part no. PSD-3R305S T102 Voltage Regulator NCP500SN50T1 X101 Connector MC1,5/5-G-3,81 Table 14: BOM DeviceNet Circuit More about DeviceNet circuits can be found on: Æ Page 118 chapter 4.11 Fieldbus Interface Æ Page 124 chapter 4.11.5 DeviceNet Interface Æ Page 126 chapter 4.11.7 Fieldbus Status LEDs netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public J I H G F E D C B 1 Checked Edited Date Name Date Name PIO5 PIO4 XM2_RX XM2_TX XM2_IO0 2 17.11.2011 Matthias Melzer GND +3V3 2 3 1 470 0603 R1042 270 0603 R1032 1 2 0805 Z=1000 Ohm @100MHz 1 R102 2 0805 Z=1000 Ohm @100MHz 1 R101 3 C101 C103 1 green 1210 VDD1 4 3 6 5 1 2 +3V3 RE R D DE T101 IL3585E K101 5V DC 4 www.hilscher.com 5 VDD2 16 0 7 12 13 10 2 6 C102 C104 ISOGND_DP 7 0805 22uF 1 PB_RXTX_P PB_RXTX_N 2 0603 100nF 1 ISO+5V_DP PROFIBUS 4 5 A B ISODE 9 GND2-1 15 GND2-2 OUT PSD-3R305S 0 IN 6 ISOLATED-AREA + 3,3V DC + 8 GND1-2 2 GND1-1 1 5 Hilscher Gesellschaft für Systemautomatiom mbH 4 3 red LEDSRG DIODE-LED-LEDSRG-1210 2 P101 2 0805 22uF 1 GND 2 0603 100nF 1 +3V3 4 8 3 1 8 EN 2 GND 5 9 NCP500SN50T1 VOUT T102 VIN 1 330 0603 1 2 2 C105 2 0805 22uF 1 100k R107 100k R106 R1052 1 9 0603 0603 10 10 ISOGND_DP ISO+5V_DP 11 11 1 2 1M R108 12 2 C106 1808 2.2nF 1 12 PE X101 13 PB_RXTX_P PB_CNTR ISOGND_DP ISO+5V_DP 14 14 Page of Page 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 PB_RXTX_N 8 9 9 10 SHIELD1 11 SHIELD2 XDCP9BW-6MM 13 1 1 J I H G F E D C B A 2.8 2010 A 1 netX100/500 Quick Start 43/158 PROFIBUS Figure 30: PROFIBUS Circuit © Hilscher, 2008-2012 netX100/500 Quick Start 44/158 Bill of Material REF DES PART TYPE PART NAME C101 Ceramic Capacitor 100 nF 25 V 0603 C102 Ceramic Capacitor 100 nF 25 V 0603 C103 Ceramic Capacitor 22 µF 6.3 V 0805 C104 Ceramic Capacitor 22 µF 6.3 V 0805 C105 Ceramic Capacitor 22 µF 6.3 V 0805 C106 Ceramic Capacitor 2.2 µF 1000 V 1808 K101 Transceiver IL3585E P101 LED red/green HSMF-C155 R101 Ferrite 100 Ω 100 MHz 1 A Würth Elektronik Part No. 74279207 R102 Ferrite 100 Ω 100 MHz 1 A Würth Elektronik Part No. 74279207 R103 Resistor 270 Ω 63 mW 0603 R104 Resistor 470 Ω 63 mW 0603 R105 Resistor 330 Ω 63 mW 0603 R106 Resistor 100 kΩ 63 mW 0603 R107 Resistor 100 kΩ 63 mW 0603 R108 Resistor 1M Ω 500 mW 2010 T101 DC/DC Step-Up PEAK part no. PSD-3R305S T102 Voltage Regulator NCP500SN50T1 X101 D-Sub9 Female SUYIN USA Part No. 070212FR009G200ZU Table 15: BOM PROFIBUS Circuit More about PROFIBUS circuits can be found on: Æ Page 118 chapter 4.11 Fieldbus Interface Æ Page 125 chapter 4.11.6 PROFIBUS Interface Æ Page 126 chapter 4.11.7 Fieldbus Status LEDs netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public J I H G F E D C 1 Checked Edited Date Name Date Name 2 28.11.2011 Matthias Melzer 2 3 3 5 SPI_CS0 AA19 Y19 AA18 Y18 AA17 Y17 AA16 Y16 AA15 Y15 AA14 Y14 AA13 Y13 W13 V13 GPIO15 W17 W16 W18 V18 V17 V16 4 www.hilscher.com 5 Hilscher Gesellschaft für Systemautomatiom mbH MICRO-NETX500-2210.000 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 IRQ/GPIO15 K2-A MICRO-NETX500-2210.000 SPI_MISO SPI_MOSI SPI_CLK SPI_CS0 SPI_CS1 SPI_CS2 K2-J SPI_MISO SPI_MOSI SPI_CLK AA19 Y19 AA18 Y18 AA17 Y17 AA16 Y16 AA15 Y15 AA14 Y14 AA13 Y13 W13 V13 GPIO15 W17 SPI_MISO W16 SPI_MOSI W18 V18 V17 SPI_CS1 V16 netX100 / 500 MICRO-NETX500-2210.000 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 IRQ/GPIO15 K1-A MICRO-NETX500-2210.000 SPI_MISO SPI_MOSI SPI_CLK SPI_CS0 SPI_CS1 SPI_CS2 K1-J netX100 / 500 4 7 GND GND +3V3 +3V3 8 1k 0603 0603 1k R2012 1 R1012 1 6 7 8 10 11 PE 9 10 9 10 1 4 7 3 5 2 6 8 COM CD NC VDD DO DI CLK CS# VSS RSV PE 11 PE1 PE 12 PE2 PE 13 PE3 PE 14 PE4 XSDCARDMICRO GPIO15 +3V3 SPI_MISO SPI_MOSI SPI_CLK SPI_CS0 GND X201 11 micro SD Card Reader PE VDD DO DI SCLK CS# GND1 GND2 10 CD_&_WP 11 COMMON 14 WP 4 7 2 5 1 3 6 PE 13 PE FPS009-2405-0 GPIO15 +3V3 SPI_MISO SPI_MOSI SPI_CLK SPI_CS1 GND GND X101 SD Card and MMC Reader Push / Push (Low Profile) 9 MMC_SD-CARD_MICRO-SD_READER 6 12 12 13 13 14 Page of Page 14 1 1 J I H G F E D C B A 2.9 B A 1 netX100/500 Quick Start 45/158 MMC/SD-Card SPI-Circuit The following figure shows the standard circuit to connect MMC/SD-Card with netX100/500. It is important GPIO15 Pin V13 of netX100/500 to connect to the MMC/SD-insert contact. Otherwise it is a normal SPI connection with chip select 1 on netX100/500 V17 pin. Figure 31: netX100/500 MMC/SD-Card SPI Circuit © Hilscher, 2008-2012 netX100/500 Quick Start 46/158 Bill of Materials MMC/SD Card REF DES PART TYPE PART NAME K1 Microcontroller netX100/500 R101 Resistor 1 kΩ 63 mW 0603 X101 MMC/SD Card reader Yamaichi Electronics Part No. FPS009-2405-0 Table 16: BOM MMC/SD Card Circuit Bill of Materials microSD REF DES PART TYPE PART NAME K2 Microcontroller netX100/500 R201 Resistor 1 kΩ 63 mW 0603 X201 microSD Card reader Amphenol Part No. GTFP08121HEU Table 17: BOM microSD Circuit More about MMC/SD-Card circuits can be found on: Æ Page 75 chapter 4.6.1.2 MMC/SD Card netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public J I H G F E D C B 1 Checked Edited Date Name Date Name 2 29.11.2011 Matthias Melzer 2 3 3 TXD2 RTS2 RXD2 CTS2 GPIO9 GPIO11 GPIO8 GPIO10 Y15 Y14 AA15 AA14 Y17 Y16 AA17 AA16 Y19 UART0_TXD Y18 UART0_RTS AA19UART0_RXD AA18UART0_CTS 5 4 www.hilscher.com 5 Hilscher Gesellschaft für Systemautomatiom mbH MICRO-NETX500-2210.000 AA13 GPIO12 Y13 GPIO13 W13 GPIO14 V13 IRQ/GPIO15 TXD1 RTS1 RXD1 CTS1 GPIO5 GPIO7 GPIO4 GPIO6 TXD0 RTS0 RXD0 CTS0 GPIO1 GPIO3 GPIO0 GPIO2 K1-A 4 UART0 UART1 UART2 A 1 C103 2 0603 100nF 1 2 6 5 4 2 14 13 15 12 C102 0603 100nF 1 UART0_TXD UART0_RTS UART0_RXD UART0_CTS C2- C2+ C1- C1+ K101 6 7 GND VCC 18 19 8 V- V+ 8 7 3 T1OUT# 17 T2OUT# 8 16 R1IN 9 R2IN MAX3232EEUP T1IN T2IN R1OUT# R2OUT# 7 UART<=>RS232 6 GND GND +3V3 RS232_TXD RS232_RTS RS232_RXD RS232_CTS 2 C104 C105 2 9 0603 100nF 1 2 0603 100nF 1 C101 0603 100nF 1 +3V3 9 0603 100 0805 10 R1322 1 3.3k R1312 1 10 11 11 PE RS232_RXD RS232_TXD RS232_DTR RS232_GND 12 1 1 2 2 3 3 4 4 5 5 6 6 7 RS232_RTS 7 8 RS232_CTS 8 9 9 10 PE SHIELD1 11 PE SHIELD2 XDCP9SW-6MM X101 12 13 13 14 Page of Page 14 1 1 J I H G F E D C B A netX100/500 Quick Start 47/158 2.10 UART Ù RS232 Figure 32: UART Ù RS232 Circuit © Hilscher, 2008-2012 netX100/500 Quick Start 48/158 Bill of Material REF DES PART TYPE PART NAME C101 Ceramic Capacitor 100 nF 25 V 0603 C102 Ceramic Capacitor 100 nF 25 V 0603 C103 Ceramic Capacitor 100 nF 25 V 0603 C104 Ceramic Capacitor 100 nF 25 V 0603 C105 Ceramic Capacitor 100 nF 25 V 0603 K1 Microcontroller netX100/500 K101 Transceiver MAX3232EEUP R131 Resistor 3.3 kΩ 63 mW 0603 R132 Resistor 100 Ω 125 mW 0805 X101 D-Sub9 Female SUYIN USA Part No. 070212FR009G200ZU Table 18: BOM UART Ù RS232 More about UART circuits can be found on: Æ Page 97 chapter 4.8 UARTs netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public J I H G F E D C 1 Checked Edited Date Name Date Name GND +3V3 2 12.01.2012 Matthias Melzer +1V5 3 A19 USB_DPOS B20 USB_DPOS B19 USB_DNEG GND 2 5 GND A B 6 4 5 SN65220DBVT R101 4 www.hilscher.com 5 Hilscher Gesellschaft für Systemautomatiom mbH MICRO-NETX500-2210.000 USB_VSS 4 USB_DNEG K1-L D18 USB_VDDIO C19 USB_VDDC 3 1 7 2 1.5k R106 GND 1 3 6 7 8 R1052 22 0603 R1042 1 120 0603 R1082 1 9 9 USB_DPOS 1 0603 22 R107 BZX84C3V3 8 USB_DEVICE_MODE 6 0603 B 2 Zener A 1 10 10 11 GND 11 PE 12 12 1 VBUS 2 D3 D+ 4 GND 5 SHIELD1 6 SHIELD2 XUSB4BW X101 13 USB-A 13 14 Page of Page 14 1 1 J I H G F E D C B A netX100/500 Quick Start 49/158 2.11 USB Device Mode Figure 33: USB Device Mode Circuit © Hilscher, 2008-2012 netX100/500 Quick Start 50/158 Bill of Material REF DES PART TYPE PART NAME K1 Microcontroller netX100/500 R101 Diode SN65220DBVT R104 Resistor 22 Ω 63 mW 0603 R105 Resistor 22 Ω 63 mW 0603 R106 Resistor 1.5 kΩ 63 mW 0603 R107 Diode BZX84C3V3 R108 Resistor 120 Ω 63 mW 0603 X101 Connector USB B Connector Table 19: BOM USB Device Circuit More about USB circuits can be found on: Æ Page 98 chapter 4.9 USB netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public J I H G F E D C 1 Checked Edited Date Name Date Name 2 29.11.2011 Matthias Melzer +1V5 GND +3V3 3 A19 4 B20 USB_DPOS B19 USB_DNEG AA19 Y19 AA18 Y18 AA17 Y17 AA16 Y16 AA15 Y15 AA14 Y14 AA13VUSB_ON Y13 USB_OC W13 V13 5 SN65220DBVT GND 4 www.hilscher.com 5 1 2 C101 15k R102 GND 2 0603 100nF 1 +5V 7 1 2 15k 6 7 GND 0603 R1052 22 USB_DPOS 1 0603 22 8 GND R1042 1 1 6 OUT1 7 OUT2 8 OUT3 TPS2041ADR 4 EN 5 OC R103 8 K101 2 IN1 3 IN2 USB_HOST_MODE R101 2 5 GND 6 A B 6 4 Hilscher Gesellschaft für Systemautomatiom mbH MICRO-NETX500-2210.000 USB_VSS USB_DPOS USB_DNEG K1-L MICRO-NETX500-2210.000 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 IRQ/GPIO15 K1-A D18 USB_VDDIO C19 USB_VDDC 3 0603 B 2 0603 A 1 2 C102 9 0603 100nF 1 9 2 10 C103 Tantal 47uF 1 10 11 GND 11 PE 12 12 1 VBUS 2 D3 D+ 4 GND 5 SHIELD1 6 SHIELD2 XUSB4BW X101 13 USB-A 13 14 Page of Page 14 1 1 J I H G F E D C B A netX100/500 Quick Start 51/158 2.12 USB Host Mode Figure 34: USB Host Mode Circuit © Hilscher, 2008-2012 netX100/500 Quick Start 52/158 Bill of Material REF DES PART TYPE PART NAME C101 Ceramic Capacitor 100 nF 25 V 0603 C102 Ceramic Capacitor 100 nF 25 V 0603 C103 Tantalum Capacitor 47 µF 10 V K1 Microcontroller netX100/500 K101 Current-Limited PowerDistribution Switch Texas Instruments Part No. TPS2041 ADR R101 Diode SN65220DBVT R102 Resistor 15 kΩ 63 mW 0603 R103 Resistor 15 kΩ 63 mW 0603 R104 Resistor 22 Ω 63 mW 0603 R105 Resistor 22 Ω 63 mW 0603 X101 Connector USB A Connector Figure 35: BOM USB Host Mode Circuit More about USB circuits can be found on: Æ Page 98 chapter 4.9 USB netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public J I H G F E D C Edited Name 1 Checked Date Name Date 2 30.11.2011 Matthias Melzer POR 3 ETM_PSTAT0 ETM_PSTAT1 ETM_PSTAT2 ETM_TCLK ETM_TSYNC ETM_DREQ ETM_DACK PIO8 PIO12 PIO11 PIO28 PIO18 PIO24 PIO27 V14 U14 U16 U13 U17 W8 W10 V9 Y8 JT_TDI JT_TDO JT_TMS JT_TCLK JT_TRST ETM_TCLK ETM_TSYNC ETM_DREQ ETM_DACK W12 ETM_PSTAT0 Y11 ETM_PSTAT1 AA11ETM_PSTAT2 AA10ETM_TPKT0 Y10 ETM_TPKT1 AA9 ETM_TPKT2 Y9 ETM_TPKT3 AA8 ETM_TPKT4 W9 ETM_TPKT5 U8 ETM_TPKT6 V8 ETM_TPKT7 V12 ETM_TPKT8 U12 ETM_TPKT9 V11 ETM_TPKT10 W11 ETM_TPKT11 U11 ETM_TPKT12 V10 ETM_TPKT13 U10 ETM_TPKT14 U9 ETM_TPKT15 4 www.hilscher.com 5 Hilscher Gesellschaft für Systemautomatiom mbH MICRO-NETX500-2210.000 JT_TDI JT_TDO JT_TMS JT_TCLK JT_TRST K1-M MICRO-NETX500-2210.000 ETM_TPKT0 ETM_TPKT1 ETM_TPKT2 ETM_TPKT3 ETM_TPKT4 ETM_TPKT5 ETM_TPKT6 ETM_TPKT7 ETM_TPKT8 ETM_TPKT9 ETM_TPKT10 ETM_TPKT11 ETM_TPKT12 ETM_TPKT13 ETM_TPKT14 ETM_TPKT15 PIO16 PIO17 PIO21 PIO22 PIO26 PIO23 PIO30 PIO29 PIO9 PIO10 PIO14 PIO13 PIO15 PIO19 PIO20 PIO25 K1-G 5 6 7 8 9 6 7 8 9 10 EMBEDDED_TRACE_MACROCELL_(ETM) +3V3 10 12 19 11 17 15 21 9 JT_TDI JT_TDO JT_TMS JT_TCLK JT_TRST POR 14 12 30 28 26 24 22 20 18 16 37 35 33 31 29 27 25 23 38 36 34 6 32 7 8 ETM_TPKT0 ETM_TPKT1 ETM_TPKT2 ETM_TPKT3 ETM_TPKT4 ETM_TPKT5 ETM_TPKT6 ETM_TPKT7 ETM_TPKT8 ETM_TPKT9 ETM_TPKT10 ETM_TPKT11 ETM_TPKT12 ETM_TPKT13 ETM_TPKT14 ETM_TPKT15 ETM_PSTAT0 ETM_PSTAT1 ETM_PSTAT2 ETM_TCLK ETM_TSYNC ETM_DREQ ETM_DACK 11 ETM9 VCC VTREF TDI TDO TMS TCK TRSTN SRSTN ETM9 GND1 GND2 GND3 GND4 GND5 GND6 TRACEPKT0 TRACEPKT1 TRACEPKT2 TRACEPKT3 TRACEPKT4 TRACEPKT5 TRACEPKT6 TRACEPKT7 TRACEPKT8 TRACEPKT9 TRACEPKT10 TRACEPKT11 TRACEPKT12 TRACEPKT13 TRACEPKT14 TRACEPKT15 PIPESTAT0 PIPESTAT1 PIPESTAT2 TRACECLK TRACESYNC DBGRQ DBGACK X101 5 40 41 42 43 44 12 ETM Connector 11 GND 13 13 Page 14 1 14 Page of 1 J I H G F E D C B 4 B 3 A 2 A 1 netX100/500 Quick Start 53/158 2.13 Embedded Trace Macrocell (ETM) Figure 36: ETM Circuit © Hilscher, 2008-2012 netX100/500 Quick Start 54/158 Bill of Materials REF DES PART TYPE PART NAME K1 Microcontroller netX100/500 X101 Connector TE connectivity Part No. 2-767004-2 Table 20: BOM ETM Circuit More about debug and test interface circuits can be found on: Æ Page 70 chapter 4.5.1 JTAG Interface Æ Page 71 chapter 4.5.2 ETM Interface Æ Page 72 chapter 4.5.3 Boundary Scan netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 J I H G F E D C B POR [1] 1 checking draw <Checked Date> Date 2 <Checked By> 08.12.2011 Matthias Melzer Name Date Name LCD_TPYL [1,2] LCD_TPYU [1,2] LCD_TPXL [1,2] LCD_TPXR [1,2] LCD_DO LCD_D1 LCD_D2 LCD_D3 LCD_D4 LCD_D5 LCD_D6 LCD_D7 LCD_D8 LCD_D9 LCD_D1O LCD_D11 LCD_D12 LCD_D13 LCD_D14 LCD_D15 LCD_D16 LCD_D17 LCD_LP LCD_FP LCD_AC LCD_CP LCD_POWER 3 MICRO-NETX500-2210.000 SPI_MISO SPI_MOSI SPI_CLK SPI_CS0 SPI_CS1 SPI_CS2 K1-J MICRO-NETX500-2210.000 PIO8 PIO9 PIO10 PIO11 PIO12 PIO13 PIO14 PIO15 PIO16 PIO17 PIO18 PIO19 PIO20 PIO21 PIO22 PIO23 PIO24 PIO25 PIO26 PIO27 PIO28 PIO29 PIO30 K1-G MICRO-NETX500-2210.000 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 IRQ/GPIO15 K1-A netX500 4 W17 W16 W18 V18 V17 V16 LCD_PCI GND 5 65795 Hattersheim Rheinstrasse 15 Hilscher GmbH LCD_TPYL LCD_TPYU LCD_TPXL LCD_TPXR POR SPI_CS2 SPI_MOSI SPI_CLK W12 LCD_R0 V12 LCD_R1 U12 LCD_R2 AA11 LCD_R3 Y11 LCD_R4 W11 LCD_R5 V11 LCD_G0 U11 LCD_G1 AA10 LCD_G2 Y10 LCD_G3 W10 LCD_G4 V10 LCD_G5 U10 LCD_B0 AA9 LCD_B1 Y9 LCD_B2 W9 LCD_B3 V9 LCD_B4 U9 LCD_B5 AA8 LCD_HSYNC Y8 LCD_VSYNC W8 V8 LCD_DLCK U8 LCD_PCI AA19 Y19 AA18 Y18 AA17 Y17 AA16 Y16 AA15 Y15 AA14 Y14 AA13 Y13 W13 LCD_BLPWM V13 2 C104 4 5 GND 2 1 SW 3 FB FAN5330SX SHDN VIN T101 10µH R102 1 LCD-BUS 7 GND 2 1 2 1 2 10 1 2 1210 6 7 8 470NF 1 10uF 1 2 2 9 10 BZV55C24 R106 GND +3V3 10 LCD_VCTRL C101 10k R101 C103 GND 2 0805 1 2 0603 100nF 1 9 C105 C102 0603 100nF R105 PMEG4005 R104 22 R103 8 LCD-MODUL-CONNECTOR LCD_PCI 0805 22uF 1 +3V3 6 2 5 1 4 3 4 LCD_BLPWM 0603 3 11 36 LCD_VCTRL 12 Anode Cathode LCD_TPYL LCD_TPYU LCD_TPXL LCD_TPXR LCC_VDD +3V3 +3V3 +3V3 GND GND GND GND GND GND GND LCD_VCTRL LCD_DCLK LCD_R0 LCD_R1 LCD_R2 LCD_R3 LCD_R4 LCD_R5 LCD_G0 LCD_G1 LCD_G2 LCD_G3 LCD_G4 LCD_G5 LCD_B0 LCD_B1 LCD_B2 LCD_B3 LCD_B4 LCD_B5 LCD_HSYNC LCD_VSYNC SPI_CLK SPI_MOSI SPI_CS POR NC NC FH23-45S-0.3SHW(05) 34 37 44 45 40 42 39 41 3 4 5 6 1 2 7 12 31 38 43 11 LCD_DLCK 32 33 35 8 X101 25 26 27 28 29 30 19 20 21 22 23 24 13 14 15 16 17 18 9 10 LCD_TPYL LCD_TPYU LCD_TPXL LCD_TPXR 12 13 13 14 14 Page of Page NL2432HC22-41KE TFT-NL2432HC22-41KE TFT-Display P101 Display DISPLAY CONNECTOR LCD_R0 LCD_R1 LCD_R2 LCD_R3 LCD_R4 LCD_R5 LCD_G0 LCD_G1 LCD_G2 LCD_G3 LCD_G4 LCD_G5 LCD_B0 LCD_B1 LCD_B2 LCD_B3 LCD_B4 LCD_B5 LCD_HSYNC LCD_VSYNC SPI_CLK SPI_MOSI SPI_CS2 POR 11 FOR NEC DISPLAY NL2432HC22-41K A 2 0603 1 2 5 6 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public 0603 1 2 1 J I H G F E D C B A netX100/500 Quick Start 55/158 2.14 LCD Interface Figure 37: LCD Interface Circuit © Hilscher, 2008-2012 J I H G F E D C B A 1 Checked Edited V20 T20 V21 T21 K1-C Date Name Date Name K201-A AGND U20 XM3_TX U21 XM3_RX U19 TP-X_ON XM3_IO0 U18 TP-Y_ON XM3_IO1 R20 XM2_TX R21 XM2_RX R19 XM2_IO0 R18 XM2_IO1 P20 XM1_TX P21 XM1_RX P19 XM1_IO0 P18 XM1_IO1 N20 XM0_TX N21 XM0_RX N19 XM0_IO0 N18 XM0_IO1 2 08.12.2011 Matthias Melzer MICRO-NETX500-2210.000 XC3 XM3_ECLK XC2 XM2_ECLK XC1 XM1_ECLK XC0 16 +3V3A 3 3 VCC POWER BOX GND 8 NLAS44599DT netX500 XM0_ECLK [1] LCD_TPYL [1] LCD_TPYU [1] LCD_TPXL [1] LCD_TPXR 2 K201-B 1 GND 2 100k 1 NC_D1 NO_D0 NC_C1 NO_C0 NC_B1 NO_B0 NC_A1 NO_A0 R209 NLAS44599DT COM_D COM_C SELECT_CD K201-C NLAS44599DT COM_B COM_A SELECT_AB 5 GND 2 100k +3V3A R210 15 13 11 9 7 5 3 1 +3V3A 4 www.hilscher.com 5 Hilscher Gesellschaft für Systemautomatiom mbH 14 10 12 6 2 4 4 0603 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public 0603 C201 C203 3 3 7 BAR43S R205 BAR43S R201 6 7 TOUCHPANEL/ADC AGND 2 0603 100nF 1 AGND 2 0603 100nF 1 6 2 1 2 1 1 8 1 2 0603 220k R206 220k R202 8 GND +3V3 2 0603 2 1 2 BAR43S R207 R211 3 3 BAR43S R203 9 9 0 1206 R212 2 1 1 0603 10 1k 0603 2 C205 10 1206 10uF 1 R2082 TP_YP-F 1 1k R2042 TP_XP-F 1 +3V3A 2 0805 Z=1000 Ohm @100MHz 1 C202 1 2 AGND 2 C206 11 0603 100nF 1 1k R2132 1 0603 C204 0603 47nF +3V3A 2 0603 47nF 1 11 2 C207 12 0603 100nF 1 AGND +3V3A 12 K1-D AGND AGND 14 13 14 Page of Page MICRO-NETX500-2210.000 V3 AD1_VREFM U4 AD1_VSS +3V3A W4 AD1_VDDIO AD_VREFP AA3 AD1_VREFP Y3 AD1_IN0 W3 AD1_IN1 TP_XP-F V4 AD1_IN2 TP_YP-F U5 AD1_IN3 AGND AA4 AD0_VREFM AGND Y4 AD0_VSS +3V3A W6 AD0_VDDIO AD_VREFP V6 AD0_VREFP AA5 ADO_IN0 Y5 ADO_IN1 W5 ADO_IN2 V5 ADO_IN3 netX500 13 ADU0 ADU1 1 2 2 J I H G F E D C B A netX100/500 Quick Start 56/158 Figure 38: Touch Panel Circuit © Hilscher, 2008-2012 netX100/500 Quick Start 57/158 Bill of Material Page 1 REF DES PART TYPE PART NAME C101 Ceramic Capacitor 10 µF 6.3 V 0805 C102 Ceramic Capacitor 100 nF 25 V 0603 C103 Ceramic Capacitor 100 nF 25 V 0603 C104 Ceramic Capacitor 22 µF 6.3 V 0805 C105 Ceramic Capacitor 470 nF 50 V 1210 K1 Microcontroller netX500 P101 LC-Display NEC NL2432HC22-41K R101 Resistor 10 kΩ 63 mW 0603 R102 Inductor Sumida CR32NP-100K R103 Diode Philips Semiconductors PMEG4005AEV R104 Resistor 22 Ω 63 mW 0603 R105 Resistor 10 Ω 63 mW 0603 R106 Diode Philips Semiconductors BZV55C24 T101 Step-up Fairchild Semiconductor FAN5330 X101 Connector Hirose Connectors Part No. FH23-45S-0.3SHW(05) Table 21: BOM LCD Interface Circuit Page 2 REF DES PART TYPE PART NAME C201 Ceramic Capacitor 100 nF 25 V 0603 C202 Ceramic Capacitor 47nF 50 V 0603 C203 Ceramic Capacitor 100 nF 25 V 0603 C204 Ceramic Capacitor 47nF 50 V 0603 C205 Ceramic Capacitor 10 µF 10 V 1206 C206 Ceramic Capacitor 100 µF 25 V 0603 C207 Ceramic Capacitor 100 nF 25 V 0603 K201 IC-Switch NLAS44599DT R201 Diode ST Microelectronics BAR43S R202 Resistor 220 kΩ 63 mW 0603 R203 Diode ST Microelectronics BAR43S R204 Resistor 1 kΩ 63 mW 0603 R205 Diode ST Microelectronics BAR43S R206 Resistor 220 kΩ 63 mW 0603 R207 Diode ST Microelectronics BAR43S R208 Resistor 1 kΩ 63 mW 0603 R209 Resistor 100 kΩ 63 mW 0603 R210 Resistor 100 kΩ 63 mW 0603 R211 Inductor Würth Elektronik Part No. 74279205 R212 Resistor 0 Ω 250mW 1206 R213 Resistor 1 kΩ 63 mW 0603 Table 22: BOM Touch Panel Circuit netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 netX100/500 Quick Start 58/158 More about LCD and touch panel circuits can be found on: Æ Page 134 chapter 4.15 LCD Interface Æ Page 135 chapter 4.16 Touch Panel Interface netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Resource Overview 3 59/158 Resource Overview The following tables list netX Hardware Resources and functions and provide information on existing software support for these features. “No driver available” means, that Hilscher does currently not provide a driver or special functions for easy access to the corresponding resource, however this resource may of course still be used if the user develops the appropriate code by himself or integrates third party products (e.g. Flash File System for parallel FLASH). 3.1 rcX Operating System Resource/Functionality netX Loadable Firmware Linkable Object Modules USB Device 100/500 for firmware update for firmware update/debug USB Host 100/500 not supported no driver available UART0 100/500 for firmware update for firmware update/debug UART1 100/500 Modbus RTU supported UART2 100/500 Modbus RTU supported SDRAM 100/500 required (min. 8MB) required (min. 8MB) for standard application Secure Memory 100/500 required (min. required see Table 25) required (min. required see Table 25) SPI Flash 100/500 required (minimum size see separate list) required (minimum size see separate list) MMC/SD Card 100/500 not supported no driver available Parallel FLASH 100/500 not supported - no FLASH File System - only limited components LC-Display 500 not supported no driver available Fieldbus Slave (1 Channel) 100/500 see Table 25 see Table 25 Fieldbus Master (1 Channel) 100/500 see Table 25 see Table 25 Ethernet Ports 100/500 RTE protocols (see separate list) Standard Ethernet and RTE protocols (see separate list) Host Interface 100/500 DPM interface DPM, Extension Bus, PCI Real Time Clock 500 not supported no driver available Gateway Functionality 100/500 not supported user programmable 2 Channel Fieldbus 100/500 not supported supported AD Converter 100/500 not supported no driver available PWM Interface 100/500 not supported no driver available Encoder Interface 100/500 not supported no driver available Table 23: List of Resources – rcX OS netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Resource Overview 3.2 60/158 Third Party Operating Systems Resource/Functiona netX Linux BSP CE BSP VxWorks BSP lity USB Device 100/500 no driver available supported no driver available USB Host 100/500 no driver available supported (max. 7 pipes) no driver available UART0 100/500 - required by uboot - remote console or standard serial port Debug or Standard port - required by eboot supported UART1 100/500 supported supported supported UART2 100/500 supported supported supported SDRAM 100/500 required (min. 32 MB with LCD) required (min. 32 MB with LCD) required (min. 8 MB, rec. 16 MB) Secure Memory 100/500 Ethernet MAC Addresses supported Ethernet MAC Addresses and user zone SPI Flash 100/500 no driver available no driver available - Flash File System (for AT45DB321C) - wear leveling provided MMC/SD Card 100/500 supported supported no driver available LC-Display 500 supported supported no driver available Fieldbus Slave (1 Chanel) 100/500 no stacks available no stacks available no stacks available Fieldbus Master (1 Chanel) 100/500 no stacks available no stacks available no stacks available Ethernet Ports 100/500 Standard Ethernet only Standard Ethernet only Standard Ethernet only Host Interface 100/500 PCMCIA interface (no support of bootable media) Extension Bus or PCMCIA interface (no support of bootable media) no driver available Real Time Clock 500 supported supported no driver available AD-Converter 100/500 no driver available driver for Touch panel only no driver available PWM Interface 100/500 no driver available no driver available no driver available Encoder Interface 100/500 no driver available no driver available no driver available rd Table 24: List of Resources – 3 Party OS netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Resource Overview 3.3 61/158 Memory Requirements of Hilscher Stacks The following table lists all field bus and RTE protocols that are currently (status of February 2011) available as Loadable Firmware or Loadable Object Modules from Hilscher, along with the required size of the SPI FLASH, holding the appropriate firmware. The FLASH size information is based on the code sizes of the current Firmware Releases, include the additional memory required for the Hilscher second stage loader (currently 52 K) and the FLASH disk, leave some headroom for future extensions and are generally rounded up to the next available FLASH size step. If Linkable Object Modules are to be used, users must of course consider the additional memory required for their user application (where applicable). All listed protocols also require different amounts of SDRAM, however the smallest available SDRAM components are meanwhile 8 MB anyway. This amount of memory meets the requirements of all current protocols and is hence indicated as minimum SDRAM size for netX designs. Loadable Firmware/LOM netX SPI FLASH size ASi Master 100/500 2MB CANopen Slave 100/500 2MB CANopen Master 100/500 2MB DeviceNet Slave 100/500 2MB DeviceNet Master 100/500 2MB CC-Link Slave 100/500 2MB PROFIBUS Slave 100/500 2MB PROFIBUS Master 100/500 2MB EtherCAT Slave 100/500 2MB EtherCAT Master 100/500 2MB Ethernet/IP Adapter 100/500 2MB Ethernet/IP Scanner 100/500 2MB Modbus RTU/TCP 100/500 2MB POWERLINK Slave (with integrated. Hub) 100/500 2MB PROFINET RT/IRT Slave (with integrated. Switch) 100/500 4MB PROFINET RT Master (with integrated. Switch) 100/500 2MB SERCOS III Slave 100/500 2MB Table 25: FLASH Sizes for Hilscher Stacks netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4 4.1 62/158 Standard Circuits RDY/RUN Pins, SYS LED The netX100 and netX500 provide two dedicated I/O pins that are used for up to two different purposes. These pins are named RDY and RUN and operate as inputs after reset. The first stage boot loader residing in the ROM of the netX chips checks the logic levels on these pins and enters certain boot modes, depending on these levels. After that, the first stage loader configures these pins as outputs, which are used to display status information. Once a firmware is started, it has complete control over these pins and their function may then be completely application specific. Note: In netX schematics, the RDY and RUN pins are usually shown with a negating circle. However, the polarity of these pins (when used as outputs) depends on a register setting. Besides the two bits that enable the output driver (pin configured as output) and set the level of the pin, there is a third bit for each pin that determines the polarity (active high or active low). So it actually depends on these polarity bits, if the (output-) pins are active low or active high! Further these polarity bits do not affect the pins when used as inputs (RDY and RUN inputs are never inverted). For historical reasons (the active low signals RDY# and RUN# were already defined for the EC1 based devices) the RDY and RUN pins are however always shown as active low. For displaying system status, a system LED (dual LED or two single LEDs) is defined: LED Color Description RDY Yellow netX with operating system is running RUN Green User application is running without errors Table 26: RDY/RUN LED Status Basically, designers could use LEDs with other colors, however it is recommended to use the Hilscher definition (especially when interpreting blink codes for troubleshooting it is helpful if customer and support see the same colors). The most flexible circuit for netX100/500 designs is shown in the following schematic. It allows setting all possible boot modes of the netX100/500 and can usually be found on evaluation hardware: netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 63/158 R1a Bootoptions: J2 J1 Boot from the first Loader found in FLASH at Memory Controller serial EPROM at SPI - I2C - MMC W20 J2 220 220 RDY 15k R2a 15k +3.3V J1 Serial boot mode (UART0 or USB) RDY yellow J2 J1 Dual-Port Memory boot mode W21 J2 J1 J2 R2b 1.27k netX100/500 1.27k RUN RUN green R1b J1 Extension Bus boot mode GND Figure 39: netX100/netX500 RDY/RUN Circuit FAQ - Frequency Answered Questions Q1: I’m not building an evaluation board. Do I really need all these jumpers? A1: Well, that depends on the way your design intends to load its firmware. Standard design that use either a serial or parallel FLASH or an MMC card for storing the firmware, do not need J2 and R2b. Designs that use a FLASH connected to the Extension Bus (a hardly used option) or Dual-Port Memory (DPM) boot mode will require both jumpers/pull-down resistors. Q2: But I’m always using DPM boot mode, can’t I just omit J1 and R1b and replace J2 by a wire? A2: You could basically do that, but keep in mind, that you will then not be able to activate the serial boot mode for test or debug purposes. Q3: I’m using a serial or parallel FLASH to boot from. Do I need any jumpers at all? A3: Unless you want to program the FLASH before mounting and remove it for reprogramming every time you want to change the firmware, it is strongly recommended to have J1 (or a push button/switch) and R1b on your design. This allows activating the serial boot mode, which will then allow to (re-)flash the firmware. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 64/158 Q4: Your reference schematics and some documentation do not show any pull-up resistors on RDY and RUN, further the netX100/500 has internal pull-ups on RDY and RUN, so do I really need these 15 kΩ pull-ups? A4: Most designs actually work with the simplified circuit that relies on the internal pull-ups on the RDY and RUN pins, hence omit the pull-ups R1 A and R2a and use 10 kΩ pull-down resistor(s). However, due to the high tolerance of internal (on-chip) pull-up/pull-down resistors and due to the antiparallel LEDs that let the RDY and RUN signals influence each other, chances are, that such designs may not enter the desired boot mode, due to invalid logic levels on RDY and RUN. Q5: I want to control the netX boot mode by applying the appropriate logic levels through external (active) components to the RDY and RUN pins. Is that possible? A5: No. Shortly after detection of the desired boot mode by the boot loader, the loader or the firmware will use the RDY and RUN pins as outputs to drive the System LED(s) and will most likely drive against the logic levels applied by the external circuit. Besides that the System LED(s) will then not work, this will drive short circuit currents through the netX RDY/RUN pins that may damage the chip! Q6: But I’m using push-buttons for the boot mode setting and would like to debounce the signals by Schmitt trigger buffers. A6: This wouldn’t make any sense at all. Since the button(s) must already be pressed when performing a reset or powering up the system, the signals will already be stable when the first stage loader checks them. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.2 65/158 Secure EEPROM The secure EEPROM available for netX controllers can hold licensing information, MAC addresses and other information. While it is generally recommended to design in this component, it is mandatory for all designs that are to run any Hilscher Master stacks (e.g. PROFIBUS Master, EtherCAT Master) or use the PCI interface of the netX500. A detailed Application Note explaining the purpose and use of the Secure EEPROM is available on the Hilscher website. On the netX100/500, the secure EEPROM is connected to the I²C interface, as shown by the following schematic: +3.3V AT88SC0104C 1 2 3 4 NC VCC NC NC NC GND SCL SDA 8 7 0.1 µF 6 W15 5 W14 I2C_SCL I2C_SDA netX GND Other (optional) I²C components Figure 40: Sample Schematic, netX100/500 Secure Memory The netX secure memory can be connected parallel to other I²C components as shown in the schematic above. It responds to device addresses starting with 0xB(1011), hence designers have to make sure, that no other connected I²C component uses this address space. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.3 66/158 Crystals, Clock generators 4.3.1 System Clock The netX100 and netX500 all use either an internal oscillator along with an external crystal or an external oscillator for generating the 25 MHz base clock, which is then stabilized by a PLL which generates all internal Clocks of the chip, except the clock for the internal Real Time Clock (netX500 only), which is covered in the following subchapter 4.3.2. The following figure shows the clock circuits for the system clock generation: a) netX 500 netX 100 b) + 1.5V OSC-VDDC OSC-VSS OSC-XTI OSC-XTO V1 W1 V2 W2 netX 500 netX 100 + 1.5V OSC-VDDC OSC-VSS OSC-XTI OSC-XTO V1 W1 GND Rs GND + 3.3V 25 MHz 25 MHz 22 pF GND V2 W2 22 pF GND GND Figure 41: netX100/500 System Oscillator Circuit The values of the capacitors and the serial Resistor (Rs) depend on the used crystal. When using the same crystal all Hilscher netX products are equipped with, the resistor Rs will not be used (and replaced by a wire), further the capacitors should have a value of 22pF. If a different crystal is used, the data sheet of the crystal must be consulted to determine the appropriate values. The Hilscher standard netX system crystal is a CS10-25.000MAGJ-UT, manufactured by Citizen. Alternatively, an external oscillator can be used, which is then connected according to schematic b). Note: When selecting an external oscillator or a different crystal, it must be provided, that these parts have a frequency of 25 MHz with a maximum tolerance of +/- 100 ppm throughout the complete temperature range, the design will be specified for! Q1: We already stock crystals or oscillators with a different frequency or higher tolerance, can we also use these parts for the system oscillator? A1: No. The 25 MHz clock is the base for all other netX clocks and has hence influence on any timing around the netX, like SDRAM timing, Baud Rates, Ethernet timing, etc. Deviating from the specified frequency will most likely result in a system that does not work properly. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.3.2 67/158 Real Time Clock 4.3.2.1 Designs with RTC The netX500 is equipped with a Real Time Clock that can be powered separately from the rest of the chip and will then continue to run when the system is powered down. The RTC module further provides a backup feature by powering a 16K portion of the netX500 internal RAM that can preserve data. To avoid uncontrolled access to this part of the RAM as a result of a power fail, the Backup RAM will be isolated when the RTC-POK pin is pulled low. If this feature is to be used, a power supervision circuit must be connected to the main power supply. The supervision circuit must pull the RTC-POK signal low, when the main input voltage drops below a certain level. This of course does only make sense, if the power supplies are designed that way, that in case the input voltage fails, they will continue to deliver stable voltages to the 1,5 V and 3,3 V rails of the netX for a certain time, allowing the isolation process to complete safely before the power fails completely. The following figure shows the complete circuit with some options: + 3.3V + 3.3V alternative circuit Backup RAM 16 kByte Schottky, e.g. BAR43 RTC-VDDIO Power fail ~ 6µA W7 RTC-POK RTC-VDDC RTC-XTI AA7 RTC-XTO Y7 AA6 Y6 + 1.5V LDO Regulator NCP663 100 netX 500 100 nF 1F 220 Backup time: 3 days GND GND GND 32.768kHz alternative circuit 22 pF Lithium Battery 3.0 V, 25 mAh 22 pF Backup time: > 150 days GND GND GND Figure 42: netX500 RTC Circuits The NCP663 regulator is just a proposal. It has been selected, due to its low quiescent current. If the power fail/Backup RAM feature is not used, the RTC_POK pin can simply be connected to VDDIO (+3,3 V). The values for the capacitors and the serial resistor in the crystal circuit again depend on the selected crystal. The shown values are suitable for the Hilscher standard netX RTC crystal, which is a Q0.032768-JTX520-12.5-20T1-LF, manufactured by Jauch Quartz GmbH. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.3.2.2 68/158 Designs without RTC or with netX100 When making designs with the netX500 that do not make use of the RTC feature or when making designs with netX100, the RTC pins must be connected as shown in the following figure: netX 500 netX 100 Backup RAM RTC-VDDIO + 3.3V W7 + 3.3V + 1.5V 16 kByte RTC-POK RTC-VDDC RTC-XTI AA7 RTC-XTO Y7 AA6 Y6 GND Figure 43: netX100/500 RTC Unused netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.4 69/158 Power On Reset and Reset In The netX100 and netX500 provide two inputs for reset signals, the Power On Reset (PORn) and the Reset In (RSTINn). While the use of the RSTINn is optional, the Power On Reset is mandatory. Since the PORn input is equipped with a Schmitt-trigger gate, it could basically be connected to a capacitor (other pin of cap. connected to GND) and a pull-up resistor, however it is strongly recommended to connect this signal to the output of a reset generator with voltage supervision, to make sure, the netX will not be released from reset until the power supplies have reached sufficient and stable levels. Reset generator components are often available with either a push/pull or an open drain output. When the design will make use of the JTAG Interface of the netX, an open drain type should be selected, since this allows to simply connect the reset signal from the JTAG connector (which is also specified as open drain) to the output of the reset generator. Of course a pull-up resistor (e.g. 10 k) must be attached to the PORn signal when using open drain reset sources. The optional RSTINn, which is commonly used by an external host processor to reset the netX, also provides a Schmitt-trigger gate. While the netX100/500 are not equipped with an internal pullup resistor, it is recommended to tie it to VDDIO (+ 3,3 V), since this can improve EMC behavior. When placing the components during PCB design, the reset source(s) should be placed near the reset inputs of the netX, to keep the traces off the reset signals short. Routing reset signals all over the PCB may result in bad EMC behavior of the design, since ESD may cause undesired resets of the chip. Experience with several netX designs further has shown that a 1nF ceramic capacitor connected to GND and PORn, with the capacitor located close to the netX PORn pin, further improves resistivity against ESD. The following figure shows the standard reset circuits: + 3.3V alternative circuits + 3.3V 10k External Reset Source (host) RSTIN From JTAG conn. (optional) +3.3V Power on RESET RESET out Manual RESET (Open Collector / Open Drain Output) POR netX500 netX100 1nF GND Figure 44:netX Reset Circuits netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.5 70/158 Debug and Test Interfaces 4.5.1 JTAG Interface The netX100 and netX500 are equipped with a standardized JTAG Interface that allows loading, flashing and starting firmware, debugging of firmware and provides access to the Boundary Scan Test mode of the chips. Though this interface is rarely used during operation of final netX products, it is strongly recommended, to have at least retrofittable access to this interface on any netX design, especially on prototypes, even for designs where the customer does not intend to write his own software but use Hilscher loadable firmware instead. Debugging of a prototype can be somewhere between cumbersome and impossible if the JTAG interface is not accessible and for development of own netX software, a JTAG interface is essential anyway. Further, automatic testing systems used in production testing usually need access to this interface, so the JTAG interface pins should at least be connected to test points that can be contacted by prober systems. Whenever there is enough space on the design’s PCB, a standard 20 pin shrouded header with 0.1” or 2.54 mm pitch should be used for the JTAG interface, since this allows connecting standard JTAG debugging units to be plugged to the board instantly, without the need for any special cable adapters. The following figure shows the standard netX JTAG circuit: TDI TDO TMS TCK nTRST nSRST VTref Vsupply GND GND GND GND GND GND GND GND GND 10k 10k +3.3V 5 13 7 9 3 15 V14 U14 U16 U13 U17 JT_TDI JT_TDO JT_TMS JT_TCLK JT_TRST +3.3V 1 2 4 6 8 10 12 14 16 18 20 +3.3V Power on RESET RESET out Manual RESET (Open Collector / Open Drain Output) W19 POR netX500 netX100 1 nF GND GND Figure 45: netX JTAG Circuits In designs that will not require the use of the JTAG interface, the JTAG signals may be left unconnected. The internal pull-down on the JT_TRSTn will then constantly hold the JTAG interface in Reset state. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.5.2 71/158 ETM Interface The ETM Interface (Embedded Trace Macro cell) that is provided by the internal ARM CPU of the netX100/500 dramatically extends the debugging capabilities provided by the JTAG interface. It is generally recommended to implement when building netX Evaluation boards, but will most likely not be needed to debug prototype hardware. Even the 38 pin ETM board connectors (AMP Mictor 2-767004-2) are costly, let alone appropriate ETM debugging units, so implementing an ETM interface will usually only be interesting for customers that write own software for their netX design. While the ETM interface on the netX500 is shared with the LCD Controller signals, which means, that driving a display is not possible when using the ETM port and vice versa. netX500 designs driving an LC-Display, and providing an ETM connector at the same time, should provide a possibility to disconnect the display in order to avoid any negative effect on the ETM signals from the display. Also the ETM and the display connector should be located close to each other, to avoid long stubs (which may cause signal reflections) going from the connector in use to the one not in use. The ETM connector is to be wired to the netX according to the following table: Conn. ARM Signals netX Signals Pin 1 Conn. ARM Signals netX Signals Pin N.C. 2 N.C. 3 N.C. 4 N.C. 5 GND VSS 6 TRACECLK ETM_TCLK 7 DBGRQ ETM_DRQ 8 DBGACK ETM_DACK 9 nSRST Not used 10 EXTTRIG 11 TDO JT_TDO 12 VTRef VCCIO 13 RTCK Not used 14 VCC VCCIO 15 TCK JT_TCLK 16 TRACEPKT[7] ETM_TPKT07 17 TMS JT_TMS 18 TRACEPKT[6] ETM_TPKT06 19 TDI JT_TDI 20 TRACEPKT[5] ETM_TPKT05 21 nTRST JT_TRSTn 22 TRACEPKT[4] ETM_TPKT04 23 TRACEPKT[15] ETM_TPKT15 24 TRACEPKT[3] ETM_TPKT03 25 TRACEPKT[14] ETM_TPKT14 26 TRACEPKT[2] ETM_TPKT02 27 TRACEPKT[13] ETM_TPKT13 28 TRACEPKT[1] ETM_TPKT01 29 TRACEPKT[12] ETM_TPKT12 30 TRACEPKT[0] ETM_TPKT00 31 TRACEPKT[11] ETM_TPKT11 32 TRACESYNC ETM_TSYNC 33 TRACEPKT[10] ETM_TPKT10 34 PIPESTAT[2] ETM_PSTAT2 35 TRACEPKT[9] ETM_TPKT09 36 PIPESTAT[1] ETM_PSTAT1 37 TRACEPKT[8] ETM_TPKT08 38 PIPESTAT[0] ETM_PSTAT0 Table 27: ETM Signals Note: The AMP Mictor connector has four additional through-hole-pins in the center which have to be grounded for proper operation of the trace port! For the PCB layout it is recommended to have the lines for the ETM signals as short as possible (the signal delay should be < 100ps). The length of the lines should be equal to avoid different signal delays. To improve signal quality, matching resistors can be netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 72/158 placed in the signal lines (located as close as possible to the chip pins (<10mm)) to match the output impedance of the chip signal driver with the PCB trace impedance 4.5.3 Boundary Scan For automated production testing of a final netX product, it may be desirable to make use of the netX Boundary Scan feature. In that case, certain conditions must be met to allow entering the Boundary Scan test mode: The first condition refers to the logic level on the TEST pin (netX100/500: K19). The design must provide a possibility to pull this signal to high level, which activates the test modes, which can be realized by a jumper or a contact pad for the test system which then controls this signal. Further, all JTAG signals must be available to the test system (e.g. by appropriate contact pads). V14 U14 U16 U13 U17 TEST 1k K19 JT_TDI JT_TDO JT_TMS JT_TCLK JT_TRST W19 POR netX500 netX100 1 nF GND Figure 46: netX100/500 Boundary Scan JTAG/TEST Signals The 1 kΩ pull-down resistor (placed as close as possible to the netX pin) can be omitted, when the signal trace between the contact pad and the netX pin is short, as then the internal pull-down resistor (nominal 50 kΩ) is sufficient to keep the TEST signal state inactive during normal operation. The second condition refers to the state of some GPIO signals as shown in the following table. The design must provide the possibility to set the required logic levels on these signals and the levels must remain in that state throughout the complete Boundary Scan test procedure. netX100/500 Signal Pin number Signal State GPIO14 W13 Pulled high GPIO8 AA15 Pulled low or unconnected GPIO9 Y15 Pulled low or unconnected GPIO10 AA14 Pulled low or unconnected GPIO11 Y14 Pulled low or unconnected netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 73/158 Table 28: netX100/500 Boundary Scan MMIO/GPIO Signals netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.6 74/158 External Memory Basically, the netX100 and netX500 provide two different interfaces where firmware memory can be connected to: The (serial) SPI interface and the parallel FLASH/SRAM interface that shares most of its pins with the SDRAM controller. Note: When the design is to be used with loadable firmware from Hilscher, an SPI FLASH is mandatory! When connecting memory components to the parallel FLASH/SRAM/SDRAM interface, designers should always mind the capacitive load that is applied to the interface signals by the memory components. The memory interface of the netX100/500 is designed to handle a maximum load capacity of 50 pF on data- , address- and DQM3-0 lines and 25 pF on all other control signals. The capacitive load directly influences the signal timing (the higher the load, the longer the signal delay) which has limited scope with SDRAMs. Since the allowed range of operating conditions (min./max. voltage, min./max. temperature) further influences signal timing, capacity limits needed to be defined, that ensure safe operation throughout the whole voltage and temperature range. When exceeding these capacity limits, this may, to a certain amount, be compensated by two clock phase parameters of the SDRAM interface, hence such “out-of-spec-designs” are imaginable, but require careful evaluation! 4.6.1 4.6.1.1 FLASH Memory SPI FLASH SPI FLASH components consume considerably little space (SO-8 package) on the PCB, while being able to hold large firmware images of 4 MB or even greater, hence it is always recommended to add such a FLASH to any design if allowed by board size constraints. Even designs using a parallel FLASH as firmware memory or designs that receive their firmware through the DPM interface from an external host processor can benefit from an additional serial FLASH that can hold a second stage boot loader or non-volatile user data. Finally it may always simply be left unpopulated if really not used in the final product. While an SPI Flash can be connected to three different chip select signals, it must be connected to chip select 0 (SPI_CS0), when the design is to be able to boot from this SPI Flash. A standard component used by Hilscher is the AT45DB321 from ATMEL, providing a capacity of 4 MB. It is being connected as shown in the following schematics: netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 75/158 SPI_MISO SPI_MOSI SPI_CLK SPI_CS0 SPI_CS1 netX 100 SPI_CS2 netX 500 AT45DB321 W17 W16 1 W18 2 V18 3 V17 4 SI SO CLK GND RESET VCC CS WP 8 +3.3V 7 6 5 V16 0.1 µF GND GND PORn Figure 47: netX100/500 SPI Flash 4.6.1.2 MMC/SD Card Instead of or in addition to an SPI Flash, MMC/SD cards can be connected to the netX, even allowing to boot a firmware image stored on such a card. To allow booting, the MMC/SD card must be connected to SPI chip select 1 (SPI_CS1). Note: Please note, that the current ROM boot loader of the netX500 may have problems booting from certain MMC/SD cards due to timing issues (see also Errata sheet of netX500). In that case, an additional SPI Flash holding the second stage loader must be connected to SPI_CS0. To detect insertion or removal of the MMC/SD card during operation, an insertion signal has been defined, that must be pulled high when an MMC/SD card is in the socket: Function Pin name and number MMC/SD insert GPIO 15 V13 Table 29: MMC/SD Card Insertion Signal +3.3V GPIO15 V13 10k MMC_INS 9 SPI_MISO SPI_MOSI SPI_CLK SPI_CS0 netX 100 netX 500 SPI_CS1 SPI_CS2 W17 SPI_CS1 W16 W18 +3.3V V18 1 2 3 4 V17 MMC / SD 5 V16 6 7 8 0.1 μF Figure 48: netx100/500 MMC/SD Card netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 76/158 Some SD-Cards disturbs the SPI data transmission from FLASH. A solution is to disconnect the SD-Card from MOSI and MISO lines with switchable bus driver when SD-Card chip select (SPI_CS1#) is high. The Figure 49 shows a solution. +3V3 5 C101 1 0603 K101-J 100nF 2 SPI_MISO SPI_MOSI SPI_CLK SPI_CS0 SPI_CS1 SPI_CS2 W17 W16 W18 V18 V17 V16 3 GND 4 Y SPI_MISO SPI_MOSI SPI_CLK SPI_CS1# K102 VCC 2 A 1 OE# GND DO SPI_CS1# 74LVC1G125GW MICRO-NETX500-2210.000 +3V3 K103 K101-A 5 VCC GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 IRQ/GPIO15 AA19 Y19 AA18 Y18 AA17 Y17 AA16 Y16 AA15 Y15 AA14 Y14 AA13 Y13 W13 V13 1 0603 SPI_MOSI SPI_CS1# 2 1 3 GND 4 Y A C102 100nF 2 +3V3 DI OE# GND DO DI SPI_CLK SPI_CS1# 74LVC1G125GW GND R1012 1 4 7 2 5 1 3 6 VDD DO DI SCLK CS# GND1 GND2 10 CD_&_WP 11 COMMON 14 WP +3V3 MICRO-NETX500-2210.000 SD/MMC-Card X101 13 PE FPS009-2405-0 0603 1k SPI_MISO C103 +3V3 ROM 32Mbit SPI_MOSI SPI_CLK SPI_CS0# 1 MOSI 2 SCK 4 CS# 8 MISO 6 VCC WP# 5 1 0603 POR# POR# 3 RESET# GND 7 AT45DB321C-CNU C104 100nF 2 GND SPI-FLASH Figure 49: Solution, if SD Card Disturbs SPI Data Transmission from FLASH 4.6.1.3 Parallel FLASH For large firmware images that come into play with graphical operating systems like Windows CE or for applications executing code directly out of FLASH, the use of parallel FLASH is inevitable. Parallel FLASH connected to the netX may be 8-, 16- or 32 Bit wide, while two 16 Bit components may be paired for 32 Bit wide access. Note: rcX does not support parallel flash. It can no file operations are executed with rcX. Though 16 Bit wide components are most common, for performance reasons 32 Bit components should be used when executing code directly out of FLASH. The netX SRAM/FLASH memory controller provides three different chip select signals (MEM_CS[2:0]), allowing to select three different memory components or pairs of components (two netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 77/158 paired 16 Bit FLASHes use a common chip select signal), each with its own set of parameters (timing and bus width). When the design is to boot from parallel FLASH, chip select 0 must be used for selecting this FLASH. The memory controller is designed to never “waste” any address lines, regardless of the bus width setting. Hence in 8 Bit mode, address line A0 is used for low and high Byte selection, while in 16 Bit mode A0 selects low and high word and in 32 Bit mode, A0 is simply the LSB of a DWORD address. For that reason, the data sheet of the desired FLASH component must be consulted, to determine the correct way of hooking up the address lines of the FLASH. Many (16 Bit-) FLASH components (e.g. TE28F128J...) use address line A0 for low/high Byte selection when operating the component in 8 Bit mode and do not use A0 at all when in 16 Bit mode. Such components must hence have A0 of the FLASH grounded (to prevent floating), while A0 of the netX is connected to A1 of the FLASH, A1 to A2, A2 to A3, etc. The following schematics show an example: netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 78/158 FLASH 16Mx16 A0 A1-24 MEM_A0-23 MEMSR_CS0n MEMSR_OEn MEMSR_WEn RST_OUTn CS OE WE BYTE VPEN RP MEM_D0-15 D0-15 +3.3V +3.3V netX (e.g. TE28F128J..) FLASH 16Mx16 A0 A1-24 MEM_A0-23 MEMSR_CS0n MEMSR_OEn MEMSR_WEn +3.3V +3.3V RST_OUTn MEM_D0-15 MEM_D16-31 CS OE WE BYTE VPEN RP D0-15 (e.g. TE28F128J..) netX FLASH 16Mx16 A0 A1-24 +3.3V +3.3V CS OE WE BYTE VPEN RP D0-15 Figure 50: netX FLASH - Address Line A0 for Low/High Byte Selection netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 79/158 Other FLASH components (e.g. S29GL256P...) always use A0 as the LSB of a Word (16 Bit-) address, hence the address lines of such components must be connected straight forward as shown in the following example schematics: FLASH 16Mx16 MEM_A0-23 A0-23 MEMSR_CS0n MEMSR_OEn MEMSR_WEn +3.3V +3.3V RST_OUTn MEM_D0-15 netX CS OE WE BYTE VPEN RESET D0-15 (e.g. S29GL256P..) FLASH 16Mx16 MEM_A0-23 A0-23 MEMSR_CS0n MEMSR_OEn MEMSR_WEn +3.3V +3.3V RST_OUTn MEM_D0-15 MEM_D16-31 CS OE WE BYTE VPEN RESET D0-15 (e.g. S29GL256P..) netX FLASH 16Mx16 A0-23 +3.3V +3.3V CS OE WE BYTE VPEN RESET D0-15 Figure 51: netX FLASH - A0 as the LSB of a Word Address netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 80/158 Q1: I would like to access parallel FLASH connected to the netX by another processor (e.g. host processor) while the netX does not use the FLASH or is being held in reset. Is that possible? A1: This will only work with additional components. Since memory interfaces are usually not designed for multi-master access, the netX always drives all of the memory interface signals, except the data lines, even while being held in reset state. Hence accessing any memory components by another processor is only possible when the memory components can be isolated from the netX memory interface by appropriate bus switches. Q2: Do I need any pull-up or pull-down resistors on the netX memory interface? A2: Since the netX always drives all of the memory interface signals, except the data lines, such resistors will only make any sense on the data signals. If no memory components are connected to the FLASH/SRAM/SDRAM interface of a netX100/500 design, then pull-ups or pull-downs on the data lines will avoid possible cross currents and may hence reduce power consumption. If only 16 Bit components are used, this applies to the upper 16 data lines. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.6.2 81/158 SDRAM Most netX applications will require the use of SDRAM, since most of the internal RAM is usually occupied by the standard 64 kB DPM and buffers, leaving only little space for quite simple applications. For certain slave applications, an alternative to using SDRAM may be the use of parallel FLASH, while the firmware is directly executed out of this FLASH instead of copying the firmware from FLASH to RAM and executing from there (which is the standard situation). SDRAM components connected to netX may be either 16 Bit or 32 Bit wide, while two 16 Bit components may be paired to allow 32 Bit wide access. Using two 8 Bit components (paired for 16 Bit) or four 8 Bit components (32 Bit) is also possible. When using SDRAM, 32 Bit wide designs are generally recommended, to make use of the full performance of the memory controller. The use of one 32 Bit wide component instead of two 16 Bit (or four 8 Bit-) components is further recommended, due to easier PCB design and reduced load capacity (two 16 Bit components usually add twice the load to the address and control signals as a comparable 32 Bit component). Q1: In the meantime DDR-3 RAM is state of the art. Why are the netX chips only equipped with an outdated SDRAM interface? A1: Well, SDRAM isn’t really outdated. DDR RAM technology was invented for the short-lived PC market, where it is commonly accepted, that components have extremely short life cycles, limited operating condition range and substantial power consumption. Since DDR RAMs work with internal PLLs and can hence not be used on older (slower) memory interfaces, DDR RAM technology is not suitable for the embedded/industrial market where customers usually look for availability of several years. Further even powerful embedded processor technology like ARM can necessarily not compete with common PC processors in terms of processing power, hence it would make little sense to connect such processors to DDR RAMs anyway. Connecting SDRAM to the netX is pretty straight forward, besides address lines A16 and A17, which are used for the bank select signals BA0 and BA1. The schematics on the following page show examples for connecting 8-, 16- and 32 Bit SDRAMs: netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 82/158 SDRAM 32Mx16 SDRAM 16Mx32 A0-12 BA0 BA1 MEM_A0-12 MEM_A16 MEM_A17 RAS CAS CS WE DQML DQMH MEMDR_RASn MEMDR_CASn MEMDR_CSn MEMDR_WEn MEM_DQM0 MEM_DQM1 CLK CKE MEMDR_CLK MEMDR_CKE MEM_A0-12 MEM_A16 MEM_A17 A0-12 BA0 BA1 MEMDR_RASn MEMDR_CASn MEMDR_CSn MEMDR_WEn MEM_DQM0 MEM_DQM1 MEM_DQM2 MEM_DQM3 RAS CAS CS WE DQM0 DQM1 DQM2 DQM3 MEMDR_CLK MEMDR_CKE D0-15 MEM_D0-15 netX CLK CKE MEM_D0-31 D0-31 netX SDRAM 32Mx16 MEM_A0-12 MEM_A16 MEM_A17 MEMDR_RASn MEMDR_CASn MEMDR_CSn MEMDR_WEn MEM_DQM0 MEM_DQM1 MEM_DQM2 MEM_DQM3 A0-12 BA0 BA1 RAS CAS CS WE DQML DQMH MEMDR_CLK MEMDR_CKE CLK CKE MEM_D0-15 MEM_D16-31 D0-15 netX SDRAM 32Mx16 A0-12 BA0 BA1 RAS CAS CS WE DQMH DQML CLK CKE D0-15 Figure 52:netX SDRAM 1 *16 Bit, 1 * 32 Bit, 2 * 16 Bit netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 83/158 SDRAM 64Mx8 SDRAM 64Mx8 A0-12 BA0 BA1 A0-12 BA0 BA1 MEMDR_RASn MEMDR_CASn MEMDR_CSn MEMDR_WEn MEM_DQM0 MEM_DQM1 MEM_DQM2 MEM_DQM3 RAS CAS CS WE DQM RAS CAS CS WE DQM MEMDR_CLK MEMDR_CKE CLK CKE CLK CKE MEM_D0-7 MEM_D8-15 MEM_D16-23 MEM_D24-31 D0-7 D0-7 MEM_A0-12 MEM_A16 MEM_A17 netX SDRAM 64Mx8 SDRAM 64Mx8 A0-12 BA0 BA1 A0-12 BA0 BA1 RAS CAS CS WE DQM RAS CAS CS WE DQM CLK CKE CLK CKE D0-7 D0-7 Figure 53:netX SDRAM 4 * 8 Bit netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.7 84/158 Host Interface The netX100/500 provides a versatile parallel asynchronous interface, referred to as “host interface” or “HIF”, that can either be “active” (netX controls the interface and accesses other memory mapped components) or “passive” (netX behaves like a Dual Port Memory (DPM) and is accessed by an external host processor). In DPM mode, the host interface can either be 8 or 16 Bit wide. Signals that are not used for host interface operation of a design (e.g. upper address lines) can be separately configured as I/Os. The host interface always works in little endian mode. As a third mode, the netX100/500 host interface can also operate as a PCI interface (device or PCI host). Since the use of the netX PCI interface is subject to certain restrictions and requires an appropriate contract, that mode is not covered in this design guide. Please contact the Hilscher sales department if you plan to use the netX PCI interface in your design. Due to the fact that the behavior of the netX host interface is configurable to a large extent, most applications do not require any additional glue logic. The host interface signal buffers of the netX100/500 are 5 V tolerant and PCI compliant and are equipped with internal clamping diodes, to raise signal undershoot/overshoot tolerance. The cathodes of the upper clamping diodes are internally wired to three power supply pins (VDDH) that must either be connected to +3.3 V (standard designs) or +5 V (host processor uses 5 V signaling voltage). Note: The output level of the netX host interface will however always be 3.3 V and NO other signals of the netX100/500 are 5 V tolerant! Since the netX100/500 host interface pins are not equipped with internal pull-up or pull-down resistors, all signals of the HIF are floating after reset. As floating signals should generally be avoided, designers should either apply external pull-up or pull-down resistors or ensure that the firmware configures all unused pins as I/O Outputs and drives them high or low. +3.3V VDDH VDDH VDDH +5V A8 VDDH A10 VDDH A15 VDDH netX 500 netX 500 netX 100 netX 100 3.3V signalling environment A8 A10 A15 5V signalling environment Figure 54: netX100/500 VDDH Pins netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.7.1 85/158 DPM Mode In DPM mode, the host interface can be controlled by separate Read (RDn) and Write (WRn/WRLn, WRHn) signals (“Intel mode”) or by a combined R/WRn signal indicating the direction of the access and Byte strobe signals (“Motorola mode”). In “Intel mode”, either a single Write signal can be used (WRLn) or two Write signals (WRLn, WRHn) for writing to the low Byte (WRLn) and high Byte (WRHn) separately. 4.7.1.1 Address Bus In case of a 16 Bit host systems with word access the address line A0 should be connected to GND. The following table shows the decoding logic for byte and word access. BHE# A0 Function 0 0 word access 0 1 access high byte 1 0 access low byte 1 1 no access Table 30: Function Table of 16 Bit Decode Logic 4.7.1.2 Non-multiplexed mode The following schematics show some examples for common setups in non-mulitplexed mode: DPM_A0-15 A0-15 CS DPM_CSn RD WR DPM_RDn DPM_WRLn DPM_WRHn DPM_RDYn RDY/WAIT Host INT DPM_INT D0-7 DPM_D0-7 Figure 55: netX DPM Intel DPM_A0-15 CS BHE DPM_CSn DPM_BHEn RD WR DPM_RDn DPM_WRLn DPM_WRHn DPM_RDYn RDY/WAIT INT netX Host ’Intel TM interface’, 8 Bit, non multiplexed TM A0-15 D0-15 DPM_INT DPM_D0-15 netX ’Intel TM interface’, 16 Bit, non multiplexed Type Interface Circuits (1) netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 86/158 DPM_A1-15 A1-15 DPM_CSn CS DPM_RDn DPM_WRLn DPM_WRHn DPM_RDYn RD WRL WRH RDY/WAIT DPM_INT INT Host D0-15 DPM_D0-15 netX ’Intel TM interface’, 16 Bit, non multiplexed, 2 write signals (Low Byte, High Byte) Table 31: netX DPM IntelTM Type Interface Circuits (2) BS1 A1-15 DPM_A0 DPM_A1-15 UDS A1-15 DPM_A0 DPM_A1-15 CS BS0 DPM_CSn DPM_BHEn CS LDS AS DPM_CSn DPM_BHEn DPM_ALE RD/WRn RD/WRn DPM_RDn TA DTACK DPM_RDYn INT IPL0 DPM_INT D0-7 D8-15 DPM_D8-15 DPM_D0-7 Host netX D0-7 D8-15 Host MotorolaTM ColdFire, 16 Bit, non multiplexed TM Figure 56: netX DPM Motorola DPM_RDn DPM_RDYn DPM_INT DPM_D8-15 DPM_D0-7 netX MotorolaTM M68000, 16 Bit, non multiplexed Type Interface Circuits netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits XREADY 87/158 DPM_RDY XA [14:1] XWE1n/XA0 DPM_A [15:2] DPM_A1 DPM_A0 XD [15:0] DPM_D [15:0] XZCS0/6/7n DPM_CSn XRDn DPM_RDn XWE0n XINT TMS320 DPM_WRLn DPM_INT DPM_WRHn DPM_BHEn DPM_ALE netX100/500 Figure 57: Texas Instruments TMS320x2833xTM, 16 Bit, Non Multiplexed Note: The netx100/500 interprets the passed address as 8 Bit-Datum. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.7.1.3 88/158 Multiplexed Mode The netX host interface can also be operated in multiplexed mode, where the data lines are alternatingly used for data and the lower address signals. The following schematics show some examples for common setups in multiplexed mode: A8-15 CS DPM_CSn ALE DPM_ALE RD WR DPM_RDn DPM_WRLn DPM_WRHn DPM_RDYn RDY/WAIT INT Host DPM_A8-15 AD0-7 DPM_A0-15 CS BHE ALE DPM_CSn DPM_BHEn DPM_ALE RD WR DPM_RDn DPM_WRLn DPM_WRHn DPM_RDYn RDY/WAIT DPM_INT DPM_D0-7 A16-?? INT netX Host ’Intel TM interface’, 8 Bit, multiplexed AD0-15 DPM_INT DPM_D0-15 netX ’Intel TM interface’, 16 Bit, multiplexed Figure 58: netX DPM IntelTM Type Circuits, Multiplexed A8-15 DPM_A8-15 CS EN AS DPM_CSn DPM_BHEn DPM_ALE RD/WRn RDY/WAIT INT AD0-7 Host DPM_RDn DPM_RDYn DPM_INT DPM_D0-7 netX ’MotorolaTM interface’, 8 Bit, multiplexed Figure 59: netX DPM MotorolaTM Type Interface Circuit, Multiplexed netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.7.1.4 89/158 ISA Mode The netX host interface also provides a virtually glueless interface to ISA Bus or PC104 systems. The following schematic shows how to connect the host interface in that case: DPM_A0-19 A0-19 +3V3 A12-15 DPM_SELA12-15 DPM_SELA16-19 DIP-Switch or Jumper (optional, for address selection) AEN 10k BHE DPM_ALE DPM_CSn DPM_BHEn MEM_RD MEM_WR MEM_CS16 DPM_RDn DPM_WRLn DPM_WRHn IOCHRDY DPM_RDYn D0-15 DPM_D0-15 DPM_INT IRQ3-15 DIP-Switch or Jumper (for IRQ selection) RESETDRV =1 ISA Bus RESETIN netX Figure 60: netX ISA Bus Interface Circuit Since the ISA Bus requires its interface cards to perform address decoding, the netX host interface also provides an internal chip select generator that can be used instead of the DPM_CSn chip select signal. The DIP Switch or jumpers connected to signals DPM_SELA16-19 allow to set the netX DPM to a certain base address on the ISA Bus. The switches or jumpers are optional, as the host interface can also be configured to use an internally stored compare value, allowing to set the base address by firmware. The circuit shown above will result in a 64k address space occupied by the netX ISA Bus interface, which is the netX standard DPM size. However, as memory space is often scarce in ISA Bus systems, the occupied memory space of the netX may be reduced by removing connections between DPM_SELA12-15 and the corresponding A12-15. If the connection between DPM_SELA15 and A15 is removed and (optionally) DPM_SELA15 is connected to the address switch / jumpers, the memory window is reduced to 32k. If this is also done for DPM_SELA14, the window is reduced to 16k, etc. Of course every reduction of the memory window size increases the granularity of the base address setting. Please also check the following subchapter for further details on the internal chip select generator. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.7.1.5 90/158 Internal Chip Select Generator As already mentioned in the previous subchapter 4.7.1.4, the netX DPM interface can use an internal chip select generator instead of the standard DPM_CSn external chip select signal. Although this was implemented mainly to meet the requirements of ISA Bus systems, the chip select generator can also be used for standard DPM applications. The internal chip select generator, which is enabled by a certain register setting, compares the state of the host interface address lines A12 –A19 to either an internal compare value (stored in a register) or to the state of the host interface SEL_A12-19 signals. It can be configured for each address line separately, if the compare value is internal (register bit) or external (SEL_Axx). Using the external source (SEL_Axx) for an address bit, allows to either connect the SEL_Axx signal to a jumper or switch (that either set this signal high or low) or to the corresponding address line (e.g. SEL_A12 to A12, SEL_A13 to A13, etc.), which makes this address bit “don’t care” for the chip select generator. When using all 8 address Bits (A12-19) for decoding, which means that none of the SELA12-19 signals are connected to the corresponding address lines (none of the address bits are “don’t care”), this results in an addressable DPM size of only 4k, while the (external) base address of the netX DPM can be selected by applying the appropriate logic levels to the SEL_A12-19 signals or by setting the appr. Register value. Combinations are of course also possible (e.g. setting the most significant part of the base address by register value, while the rest of the address is set by jumpers/switches). Starting from the 4k minimum, the accessible DPM size can continually be doubled to the maximum of 64k (standard size), by connecting the appr. number of SEL_Axx signals to the corresponding address lines and setting the corresponding compare value source to ‘external’. Note: When reducing the addressable DPM size, please be aware of some drawbacks that come with smaller netX DPMs. Some system registers, which are “hard mapped” to the upper end of the 64k area can not be reached with a reduced DPM. Further, loadable firmware provided by Hilscher usually presumes that the full 64k area is available to the host and does hence not support designs with reduced DPM size. It is strongly recommended that hardware designers planning to reduce the addressable DPM size consult their software department, to make sure, this will not collide with the final application! The following schematics show some examples of how to connect the address and SEL_Axx lines: netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 91/158 A0-19 DPM_A0-19 A12-15 DPM_SELA12-15 DPM_SELA16 10k 10k 10k 10k 2.2k 2.2k 2.2k 2.2k DPM_SELA17 DPM_SELA18 DPM_SELA19 64k addressable Host netX +3V3 A0-19 DPM_A0-19 A12-14 10k 10k 10k 10k 10k DPM_SELA12-14 DPM_SELA15 DPM_SELA16 2.2k 2.2k 2.2k 2.2k 2.2k DPM_SELA17 DPM_SELA18 DPM_SELA19 32k addressable Host netX +3V3 DPM_A0-19 A0-19 10k 10k 10k 10k 10k 10k 10k 10k DPM_SELA12 DPM_SELA13 DPM_SELA14 DPM_SELA15 DPM_SELA16 2.2k 2.2k 2.2k 2.2k 2.2k 2.2k 2.2k 2.2k DPM_SELA17 DPM_SELA18 DPM_SELA19 4k addressable Host netX +3V3 Figure 61: netX Internal Chip Select Generator Circuits netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.7.1.6 92/158 RDY/WAIT Signal Since the DPM mode of the netX host interface provides a virtual Dual Port Memory instead of a real DPM (external accesses to the DPM are redirected to programmable memory locations inside the netX), there is no fixed access time for reading or writing the netX DPM, even when there is no access conflict. Real DPM components however also use a Busy signal to compensate access conflicts (one side of the memory reads a certain memory location while the other side tries to write the same location or vice versa). In order to make sure, that the host processor will read valid data, respectively the netX successfully accepted write data from the host, while keeping access cycles as short as possible, it is mandatory for the host processor to support a Ready or Wait signal from an external memory! To allow glueless interfaces, the netX RDY/WAIT signal supports two different basic modes (Ready mode, where an active Ready signal indicates that the cycle may now be terminated and Wait mode, where an active Wait signal indicates, that the netX is still busy and the cycle may not yet be terminated) that can either work with active high or active low signals. Further, the output of the RDY/WAIT signal can be configured as push/pull or open drain – open source with sustained tri-state option (signal edge is actively driven). For more details and diagrams please consult the appr. netX Technical Reference Guide (separate documents for netX100/500). netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.7.2 93/158 Extension Bus Mode In Extension Bus mode, the netX provides an active parallel, 8- or 16 Bit wide asynchronous bus interface with support for a Ready or Wait signal that allows external components to extend data cycles beyond the programmed cycle timing. The Extension Bus can either use separate Read (EXT_RDn) and Write (EXT_WRn/WRLn, EXT_WRHn) signals (“Intel mode”) or a combined R/WRn signal indicating the direction of the access along with Byte strobe signals (“Motorola mode”). In “Intel mode”, either a single Write signal can be used (EXT_WRLn), combined with a Byte Enable Signals (EXT_BHEn) or two Write signals (EXT_WRLn, EXT_WRHn) for writing to the low Byte (EXT_WRLn) and high Byte (EXT_WRHn) separately. The Extension Bus can be used to connect parallel peripherals like SRAMs, FLASHes, DPMs, etc. and can operate in non-multiplexed or multiplexed mode. The four different chip select signals allow to connect four completely different devices, as the configuration for each chip select area is done separately. The netX also provides the possibility to boot from a memory device connected to the Extension Bus. In that case, the device must be connected to use the EXT_CS0n chip select signal and the Extension Bus boot mode must be selected. 4.7.2.1 Non-multiplex Mode The following schematics show some examples for common setups in non-multiplexed mode: EXT_A0-24 A0-24 EXT_CS0-3n EXT_BHEn EXT_ALE CS EXT_RDn EXT_WRLn EXT_WRHn EXT_RDYn RD WR EXT_INT INT EXT_D0-7 D0-7 RDY/WAIT netX IntelTM, 8 Bit, one write signal Figure 62: netX Extension Bus IntelTM Type Interface Circuit 8Bit, non Multiplex netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits EXT_A0-24 94/158 EXT_A0-24 A0-24 EXT_CS0-3n EXT_BHEn EXT_ALE CS BHE EXT_CS0-3n EXT_BHEn EXT_ALE EXT_RDn EXT_WRLn EXT_WRHn EXT_RDYn RD WR EXT_RDn EXT_WRLn EXT_WRHn EXT_RDYn EXT_INT INT EXT_D0-15 RDY/WAIT EXT_INT EXT_D0-15 D0-15 netX A0-24 CS BHE RD WRL WRH RDY/WAIT INT D0-15 netX IntelTM, 16 Bit, one write signal IntelTM, 16 Bit, write low/high signals Figure 63: netX Extension Bus IntelTM type Interface Circuit 16Bit, non Multiplex EXT_A0-24 A0-24 EXT_A0-24 A0-24 EXT_CS0-3n CS EXT_CS0-3n CS EXT_ALE AS EXT_ALE AS EXT_RDn EXT_WRLn RD/WRn DS EXT_RDn EXT_WRLn RD/WRn DS EXT_RDYn RDY/WAIT EXT_RDYn RDY/WAIT EXT_INT EXT_D0-15 INT D0-15 netX EXT_INT INT EXT_D0-7 D0-7 netX MotorolaTM, 16 Bit, one data strobe MotorolaTM, 8 Bit, one data strobe Figure 64: netX DPM MotorolaTM Type Interface Circuits, non Multiplex 4.7.3 Multiplex Mode The netX host interface can also be operated in multiplexed mode, where the data lines are alternatingly used for data and the lower address signals. The following schematics show some examples for common setups in multiplexed mode: netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 95/158 EXT_A8-24 A8-24 EXT_CS0-3n EXT_BHEn EXT_ALE CS EXT_RDn EXT_WRLn EXT_WRHn EXT_RDYn RD WR EXT_INT INT ALE RDY/WAIT EXT_D0-7 AD0-7 netX Intel, 8 Bit, one write signal EXT_A16-24 A16-24 EXT_A16-24 A16-24 EXT_CS0-3n EXT_BHEn EXT_ALE CS BHE ALE EXT_CS0-3n EXT_BHEn EXT_ALE CS BHE ALE EXT_RDn EXT_WRLn EXT_WRHn EXT_RDYn RD WR EXT_RDn EXT_WRLn EXT_WRHn EXT_RDYn EXT_INT INT RDY/WAIT EXT_D0-15 EXT_INT EXT_D0-15 AD0-15 netX RD WRL WRH RDY/WAIT INT AD0-15 netX Intel, 16 Bit, one write signal TM Figure 65: netX DPM Intel Intel, 16 Bit, write low/high signals Type Interface Circuit, Multiplexed netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 96/158 A8-24 EXT_A16-24 A16-24 EXT_CS0-3n CS EXT_CS0-3n CS EXT_ALE AS EXT_ALE AS EXT_A8-24 EXT_RDn EXT_WRLn RD/WRn DS EXT_RDYn RDY/WAIT EXT_INT EXT_D0-7 EXT_RDn EXT_WRLn EXT_WRHn EXT_RDYn EXT_INT INT EXT_D0-15 AD0-7 netX RD/WRn BS0 BS1 RDY/WAIT INT AD0-15 netX MotorolaTM, 8 Bit, one data strobe MotorolaTM, 16 Bit, two data strobes Figure 66: netX Extension Bus MotorolaTM Interface Circuit, Multiplexed 4.7.4 External pull-ups/pull-downs, unused signals As already mentioned at the beginning of the chapter 4.7, the netX100/500 does not provide any internal pull-ups or pull-downs on the host interface signals. For that reason, any unused signals of the host interface should either be externally pulled low or high, or should be configured as outputs and be driven low or high by the firmware of the design. Since even the connected signals of the host interface may float upon reset (they are all configured as inputs by default), designers should make sure, that these initially floating signals will not cause any (start-up) problems with the host interface circuit of their design. If in doubt, add external pullups or pull-downs to ensure the appr. inactive state of the signals. The CLOCKOUT signal and the WDGACT signals should always be pulled low or high when not used, since these signals can not simply be driven low or high. The TCLK signal should always be grounded (this is a dedicated input, so grounding is not a problem). Q1: Instead of using external pull-down or pull-up resistors on unused host interface signals, can’t just tie these signals to GND or 3.3 V? A1: This is of course possible, but keep in mind, that almost all host interface pins can be configured to output mode, hence when tying such signals to GND or 3.3 V, there is always the risk of short circuit conditions, when misconfiguring the host interface (e.g. during software development). netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.8 97/158 UARTs The netX provides a total of three UARTs (each with RX, TX, RTSn, CTSn) that interface directly to common RS-232 or RS-485 transceivers, as shown in the following example schematics. UART0 is the UART that must be used when the serial boot mode via UART is to be available. UART0 may further be used as diagnostic port by Hilscher firmware. This example shows connection for UART0. UART1 and UART2 are connected equally. UART0_TXD UART0_RTSn UART0_RXD UART0_CTSn Y19 6 1 Y18 AA19 9 AA18 5 netX100 netX500 RS-232 Transceiver (e.g. MAX3232E) Figure 67: netX100/500 UART0 If UART0 is not be used and the USB port is to support the serial boot mode, then the following external pull-up resistors are required on netX100/500 UART0 pins: +3.3V GPIO03 / UART0_RTSn GPIO00 / UART0_RXD GPIO02 / UART0_CTSn Y18 10k Y19 10k GPIO01 / UART0_TXD AA19 AA18 netX100 netX500 Figure 68: netX100/500 UART0 Unused If UART0 is completely unconnected and the netX is configured for serial boot mode, then the ROM boot loader misinterprets the low level on RXD and CTSn (caused by the internal pull-downs on these unconnected pins) as a connection attempt through the UART0 port and switches to UART mode. The serial boot mode can then not be used via the USB port and can hence not be used at all (as UART0 is of course not accessible when not connected). netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.9 98/158 USB The netX provides a USB 1.1 compliant USB interface that can either be used in device mode (Downstream Port) or in host mode (Upstream Port). The device mode is commonly used to connect the netX to a PC, while the host mode allows to access for example memory devices like USB-sticks, etc. Both modes require different external circuits that are described in the following chapters. Though the netX is equipped with separate power supply pins for the USB interface (USB_VDDIO, USB_VDDC and USB_GND on the netX100/500), these pins can simply be connected to the corresponding voltage rail and do not require any special filtering etc, however please regard the following note related to the USB_VDDIO (+3.3 V) supply: Note: The worst case short circuit current that may flow through the netX USB Buffers can reach 170mA when a short circuit on the USB cable occurs. When the design is to continue working under that condition, the netX VDDIO rail (+3.3 V) must either be able to deliver this additional current, or the USB_VDDIO supply must be connected to the 3.3 V rail through an appropriate fuse or current limiter (PTC) or a separate supply! Like ALL power supply pins on the netX, the USB power supply pins must always be connected, even when the USB interface is not used! 4.9.1 4.9.1.1 Device Mode Simple Circuit The device mode is the commonly used mode of the netX USB interface and allows to connect the netX to a PC (in serial boot mode), which can then download and flash firmware, read and modify register values and run hardware test applications by the help of freely available software tools from Hilscher. In order to be able to use this handy and yet simple debug and service connection, the implementation of a USB device port is always recommended whenever allowed by board size constraints Note: With netX100/500 designs that do not use the UART0 port of the netX, please make sure, that the required pull-up resistors on UART0 are present, otherwise the serial boot mode via USB won’t work (see chapter 4.8 for details). netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits USB_VDDIO D18 +3.3V 1.5V 120 C19 USB_DPOS B20 1 VBUS BZX84C3V3 1.5k USB_VDDC 99/158 24 3 D+ 2 1 D- 3 4 SN65220D Transient Suppressor USB_DNEG B19 24 2 Receptacle „B“ USB_VSS netX100 netX500 A19 4 GND GND Figure 69: netX100/500 USB DOWNstream Port (Device Mode) The shown example schematics show the standard circuit as it is most commonly used, also with many Hilscher netX designs. Whenever a reconnect to the USB host is necessary, this circuit requires unplugging and replugging the USB cable, since USB host and netX detect a connect through the 1.5k pull-up resistor that becomes active when the cable is plugged in on both sides. If your application requires reconnecting without unplugging/replugging, the pull-up resistor must be made “switchable”, by using the advanced circuit (which allows to simulate manual plugging/unplugging), described in the following chapter. 4.9.1.2 Advanced Circuit The circuit shown in the previous subchapter is perfect when the USB port is only used along with the serial boot mode of the netX. However, when using the USB port also during normal operation of the device (e.g. for diagnostic purposes), the following problem may occur: Since the pull-up resistor on the D+ line, that lets the USB host (PC) detect the connection of a USB device (netX), is automatically activated when the netX device is plugged to the hosts USB port, chances are that the firmware of the netX device has not yet initialized the netX USB port. In that case, the host detects an unknown USB device and the USB cable needs to be disconnected and reconnected again after the netX USB port has been initialized by the firmware. If this is not acceptable, the following circuit(s) should be used: netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits USB_VDDIO USB_VDDC 100/158 D18 +3.3V 1.5V C19 Jumper 120 USB_DPOS B20 1 VBUS BZX84C3V3 1.5k GPIO12 AA13 24 3 D+ 2 1 3 4 SN65220D Transient Suppressor USB_DNEG B19 24 2 D- Receptacle „B“ USB_VSS A19 netX100 netX500 4 GND GND Figure 70: netX100/500 USB DOWNstream Port (Device Mode), Advanced Circuit When using the circuits shown above, accessing the netX through the USB serial boot mode will not work, since the serial boot mode is handled by the netX ROM loader and the ROM loader will not activate GPIO12 hence the PC will not detect a connected USB device. For that reason, the circuit includes a jumper that allows the pull-up to be connected to the 3.3 V sourced through the USB Bus. For devices where using such a jumper or a switch is not applicable, a special nonstandard diagnostic cable, including an external pull-up on D+ must be used, when the netX needs to be accessed in USB serial boot mode! 4.9.2 Host Mode In host mode, the netX500 USB port can be used to access other USB devices, like USB-Sticks, Memory Card Reader, etc. It is most commonly used along with Windows CE images but may however basically be accessed by any operating system (see chapter 3.2 for information on current driver support!). In host mode, the design must supply the +5 V bus voltage for the USB port. The most simple circuit would directly deliver the +5 V to the corresponding pin of the USB receptacle, however the use of a suitable power switch is recommended, as shown in the following example schematics. Such a power switch allows to detect short circuit or over current conditions and turn off the USB Bus voltage in such a case. It also provides the possibility to disconnect and reconnect devices, by turning off and on the bus voltage. Two additional signals for connecting such a power switch to the netX have been defined: Function Pin name and number USB power switching GPIO 12 AA3 USB over current detection GPIO 13 Y13 Table 32: Additional USB Signals GPIO12 has also been assigned another standard functionality, which however is not a conflict, since the other assignment refers to the USB device mode which can only be used alternatively to the Host mode. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 101/158 The USB Bus power switching signal (VUSB_ONn) is used to turn on and off the USB Bus power. When used, this (active low) signal is to be connected to the enable input of a power switch. The USB over current detection signal (USB_OCn) is used to signal a USB over current condition detected by the power switch to the netX. When used, this (active low) signal is to be connected to the over current output signal of a power switch. Note: Please note, that there is no inherent hardware support for the above mentioned signals. All functions associated with these signals are only available, when supported by firmware! The +5 V power supply must be dimensioned to meet the power requirements of the USB devices that are to be connected to the netX (some devices require up to 500mA when fully operational!). Please also consider the USB V1.1 specification for further details. 3.3V USB_VDDIO USB_VDDC 1.5V D18 C19 +5V Power Switch Vin GPIO12 GPIO13 AA13 Y13 VUSB_ONn EN USB_OCn OC Vout 1 VBUS (e.g. TPS2041A) USB_DPOS B20 24 3 D+ 1 2 3 4 SN65220D Transient Suppressor B19 USB_VSS netX100 netX500 2 D- Receptacle „A“ 15k 24 15k USB_DNEG A19 4 GND GND Figure 71: netX100/500 USB UPstream Port (Host Mode) netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 102/158 4.10 Ethernet Interface netX100/500 have two integrated Physical Layer Units (PHYs) for Ethernet Communication, that allow to build systems with two Ethernet ports, while using only a few external components like pull-ups and transformer(s). The PHYs can be operated in two basic modes, which are twisted pair (10BASE-T/100BASE-TX) and fiber optic mode (100BASE-FX). 4.10.1 Twisted Pair For 10BASE-T or 100BASE-TX Ethernet communication, the PHY must be connected as shown in the following example schematic (Figure 72). G18 D19 E19 F19 C2 10µ C3 100n C4 10µ 1.5V R2 1000 ȍ @ 100 MHz, 200 mA 3.3V R11 10 J20 E18 H18 H19 C6 100n PHY_VSSAT PHY_VSSACP PHY0_VSSAR PHY0_VSSAT1 PHY0_VSSAT2 PHY1_VSSAR PHY1_VSSAT1 PHY1_VSSAT2 J20 F18 C5 100n PHY_VDDIOAT PHY_VDDIOAC C1 100n R1 1000 ȍ @ 100 MHz, 200 mA R4 50 PHY_VDDCAP PHY0_VDDCART PHY1_VDDCART D20 R3 50 F17 H17 H1 RJ45 1 PHY0_TXP G21 2 PHY0_TXN G20 PHY0_RXP R12 10 R6 50 R5 50 C9 10n R15 75 R16 75 R17 75 R18 75 5 7 2 6 PHY0_RXN H20 R13 10 R8 50 R7 50 C8 100n C7 100n H2 RJ45 1 F20 F21 R14 10 R10 50 R9 50 C11 10n PHY1_RXP R19 75 R20 75 R21 75 R22 75 E21 7 2 PHY_EXTRES G19 netX100/500 GND R23 12.4k RXP RXN C14 10n / 2kV C12 10n PHY_ATP G17 TXN 5 3 E20 TXP 4 6 PHY1_RXN RXN PE 2 PHY1_TXN RXP C13 10n / 2kV C10 10n PHY1_TXP TXN 4 3 H21 TXP C15 1n / 2kV PE GND Figure 72: netX100/500 2 Channel Ethernet Circuit (Twisted Pair) netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 103/158 Component Value Tolerance Rating R1, R2 1000 Ω @ 100 MHz R3, R4, R5, R6, R7, R8, R9, R10 50 Ω 1% 125 mW R11, R12, R13, R14 10 Ω 1% 63 mW R15, R16, R17, R18, R19, R20, R21, R22 75 Ω 1% 63 mW R23 12.4 kΩ 1% 63 mW C1, C3, C5, C6, C7, C8 100 nF 6.3 V C2, C4 10 µF 6.3 V C9, C10, C11, C12 10 nF C13, C14 10 nF 2 kV C15 1 nF 2 kV H1, H2 H1102 200 mA 20% HX1188 (Pulse Eng.) TS6121C (Bothhand) Table 33: Ethernet Circuit Component Specification The selected Ethernet transformer(s) (H1, H2, the Table 33 lists three examples) must be 1:1 ratio types with center tap and should be symmetric, which means, that transmit and receive path may be swapped. This is necessary to support the auto-crossover feature that is mandatory for most Real-time Ethernet protocols! Instead of a separate transformer, secondary side resistors (75 Ω) and RJ45 jack, integrated jacks can be used, that combine all components (plus Status LEDs) in the housing of the jack. They are available as single-channel or 2-channel models. Hilscher commonly uses a 2 channel integrated jack that also includes the PE capacitor (C3a/C3b) and is available from Pulse Engineering, ERNI and Trxcom: Pulse Engineering: J8064D628AN ERNI: 203313 Trxcom: TRJ26204B netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 104/158 If only one Ethernet port is required, this port should be connected according to the following schematic: C3 100n C4 10µ R2 1000 ȍ @ 100 MHz, 200 mA 3.3V R11 10 C2 10µ 1.5V R4 50 J21 E18 H18 H19 G18 D19 E19 F19 C6 100n PHY_VSSAT PHY_VSSACP PHY0_VSSAR PHY0_VSSAT1 PHY0_VSSAT2 PHY1_VSSAR PHY1_VSSAT1 PHY1_VSSAT2 J20 F18 C5 100n PHY_VDDIOAT PHY_VDDIOAC C1 100n R3 50 F17 PHY_VDDCAP H17 PHY0_VDDCART PHY1_VDDCART D20 R1 1000 ȍ @ 100 MHz, 200 mA H1 RJ45 1 PHY0_TXP G21 2 PHY0_TXN G20 TXP TXN 4 C9 10n R15 75 R16 75 R17 75 R18 75 5 PHY0_RXP R12 10 R6 50 R5 50 7 2 3 H21 6 PHY0_RXN H20 F20 PHY1_TXN F21 PHY1_RXP E20 PHY1_RXN E21 RXN C13 10nF / 2kV C10 10n PHY1_TXP RXP GND C15 1n / 2kV PE PHY_ATP G17 netX100/500 R23 12.4k PHY_EXTRES G19 GND Figure 73: netX Single Channel Ethernet Circuit (Twisted Pair) Q1: We do not stock 12.4 kΩ resistors and/or 50 Ω resistors. Can’t we use 12 kΩ/49 Ω/51 Ω instead? A1: The specified resistor values are directly taken from the specs of the internal PHY. Using out-of-spec resistor values will result in an out-of-spec Ethernet Interface that can not be guaranteed to work properly under all conditions. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.10.2 105/158 Fiber Optic For 100BASE-FX Ethernet communication, the netX requires external optical transceivers. Since these transceivers usually work with LVPECL (Low Voltage Positive Emitter Coupled Logic) levels, appropriate signal converters must further be connected between netX and transceivers. The signal converters should be placed as close as possible to the corresponding netX pins and the traces of the differential signal lines between buffers and transceivers should provide an impedance of 50 Ω (100 Ω differential impedance). The signal lines are to be terminated with a Thevenin termination as shown in the following schematics. Transceivers without internal termination + 1.5V R1 1000 ȍ @ 100 MHz, 200 mA PHY_EXTRES netX100 netX500 PHY_ATP R7 127 R6 127 R5 127 R3 127 TXD - (IN) TXDIS R8 82.5 N18 + 3.3V H21 R12 82.5 SD - R17 127 RXD - (OUT) + R11 82.5 RXD+ (OUT) - R16 127 N19 + R10 82.5 N21 FX Transceiver GND + 3.3V H20 F21 XM1_TX XM1_RX E20 E21 netX100 netX500 XM1_IO0 XM1_IO1 P20 R15 127 GND F20 + TXD+ (IN) - P21 P19 TXD - (IN) + RXD+ (OUT) - RXD - (OUT) + SD - TXDIS P18 R22 82.5 PHY1_RXN XM0_IO1 G20 TXD+ (IN) - R21 82.5 PHY1_RXP XM0_IO0 G21 + R20 82.5 PHY1_TXN XM0_RX N20 R14 127 PHY1_TXP XM0_TX R19 82.5 PHY0_RXN GND R13 127 PHY0_RXP + 3.3V R24 1k PHY0_TXN C4 10μ R25 1.6k PHY0_TXP C3 100n + 3.3V R2 1000 ȍ @ 100 MHz, 200 mA FX Transceiver G19 G17 R23 12.4k PHY_VSSAT PHY_VSSACP PHY0_VSSAR PHY0_VSSAT1 PHY0_VSSAT2 PHY1_VSSAR PHY1_VSSAT1 PHY1_VSSAT2 J21 E18 H18 H19 G18 D19 E19 F19 C2 10μ R4 127 J20 PHY_VDDIOAT F18 PHY_VDDIOAC C1 100n R9 82.5 F17 PHY_VDDCAP H17 PHY0_VDDCART D20 PHY1_VDDCART R18 82.5 4.10.2.1 GND GND Figure 74: netX100/500 Ethernet Circuit (Fiber Optic) netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 106/158 Component Value Tolerance R3, R4, R5, R6, R7, R13, R14, R15, R16, R17 127 Ω/130 Ω 1% R8, R9, R10, R11, R12, R18, R19, R20, R21, R22 82.5 Ω/82 Ω 1% R24 1 kΩ/82 Ω R24 1.6 kΩ/130 Ω R23 12.4 kΩ C1, C3 100 nF 6.3 V C2, C4 10 µF 6.3 V R1, R2 1000 Ω @ 100 MHz 200 mA 1% Rating 125 mW Table 34: Fiber Optic Ethernet Circuit Component Specification netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.10.2.2 107/158 Transceivers with internal AC-termination Some Fiber Optic Transceivers already provide an internal AC-termination on the TXDATA input lines, which results in a slightly different circuit: + 1.5V R1 1000 ȍ @ 100 MHz, 200 mA C3 100n C4 10μ TXD+ (IN) - TXD - (IN) N21 N19 + RXD+ (OUT) - RXD - (OUT) + SD - TXDIS N18 G20 + 3.3V PHY_EXTRES netX100 netX500 PHY_ATP E21 netX100 netX500 XM1_IO0 XM1_IO1 R13 127 R12 127 + TXD+ (IN) - P21 P19 TXD - (IN) + RXD+ (OUT) - RXD - (OUT) + SD - TXDIS P18 G19 G17 FX Transceiver (e.g. AFBR-5978Z / QFBR-5978AZ ) GND R23 12.4k PHY1_RXN E20 P20 R18 82.5 XM1_TX R17 82.5 F21 XM1_RX PHY1_RXP R11 127 GND F20 R16 82.5 PHY1_TXN + 3.3V H20 R15 195 PHY1_TXP (e.g. AFBR-5978Z / QFBR-5978AZ ) GND H21 R14 195 PHY0_RXN FX Transceiver R25 1.6k PHY0_RXP R10 82.5 XM0_IO1 R5 127 R3 127 G21 + R8 82.5 XM0_RX N20 R7 195 XM0_TX R24 1k PHY0_TXN + 3.3V GND XM0_IO0 PHY0_TXP + 3.3V R2 1000 ȍ @ 100 MHz, 200 mA R6 195 PHY_VSSAT PHY_VSSACP PHY0_VSSAR PHY0_VSSAT1 PHY0_VSSAT2 PHY1_VSSAR PHY1_VSSAT1 PHY1_VSSAT2 J21 E18 H18 H19 G18 D19 E19 F19 C2 10μ R4 127 J20 PHY_VDDIOAT F18 PHY_VDDIOAC C1 100n R9 82.5 F17 PHY_VDDCAP H17 PHY0_VDDCART D20 PHY1_VDDCART GND Figure 75: netX100/500 Ethernet Circuit (Fiber Optic) Component Value Tolerance R3, R4, R5, R11, R12, R13 127 Ω/130 Ω 1% R8, R9, R10, R16, R17, R18 82.5 Ω/82 Ω 1% R6, R7, R14, R15 195 Ω 1% R19 1 kΩ/82 Ω R20 1.6 kΩ/130 Ω R23 12.4 kΩ C1, C3 100 nF 6.3 V C2, C4 10 µF 6.3 R1, R2 1000 Ω @ 100 MHz 200mA 1% Rating 125 mW Table 35: Fiber Optic Ethernet Circuit Component Specification (AC-Termination) netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits Note: 108/158 The termination resistors shall be placed as close as possible to the end of the signal lines, connected with short traces (no stubs). Due to the large number of resistors, this can hardly be accomplished with standard (0603) resistors. A special Resistor array, containing 8 resistor pairs (127 Ω pull-up, 82.5 Ω pull-down) with common GND and VCC connection in a small BGA package is available from CTS (type RT1250B7) that allows to fulfill this requirement. The BIAS resistors on the TXD signals (circuit for internally AC-terminated Transceivers) are to be placed close to the beginning of the signal line, which means close to the LVTTl-to-LVPECL level translators. Please also see the following chapter for hints on component placement. The 127 Ω/82.5 Ω Thevenin termination results in a bias voltage of 2.0 V and a signal termination of appr. 50 Ω. Alternatively, 130 Ω/82 Ω can be used. The recommended value for resistors R6, R7, R14, and R15 in the circuit for internally AC-terminated Transceivers depends on the LVTTL-to-LVPECL level translators that are used. 195 Ω is the recommended value when using devices from MICREL. When using other components please consult the device datasheet and appropriate Manufacturers application notes if available. The values for R24 and R25 are flexible. Important is only the resistor ratio that results in a voltage of 2.0 V (VCC – 1.3 V). The LVTTL-to-LVPECL signal converters usually have thermal PADs to achieve proper heat dissipation. Make sure to consider the thermal design notes in the datasheet of the appropriate devices. The power supply (+3,3 V) for the Fiber optic Transceivers should be filtered according to the manufacturer’s recommendation (consult data sheet of transceiver). Detailed schematics for netX100/500 Fiber Optic interfaces using the AFBR5978Z/QFBR-5978AZ transceivers with internal AC-termination can be found on page 29 chapter 2.2.3 Fiber Optic with AFBR-5978Z netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.10.2.3 109/158 PCB Layout considerations The following drawings provide hints on proper placement of the Fiber Optic interface components. Transceivers without internal termination +3V3 RD+ RD- Place level translators as close to netX pins as possible! Hi-Speed single ended signals. Keep traces as short as possible! TX RX SD TD+ TD- Termination resistors. Place as close to level translators as possible! Keep traces as short as possible! +3V3 Termination resistors. Place as close to FX transceiver as possible! Differential signal lines, Zdiff = 100 Ohm Keep traces as short as possible! + TXD+ (IN) - TXD - (IN) + RXD+ (OUT) - RXD - (OUT) + SD FX Transceiver - Single ended signal line, Z = 50 Ohm netX Termination resistors. Place as close to level translators as possible! +3V3 SD+ - Figure 76: netX Ethernet Circuit (Fiber Optic), Component Placement netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 110/158 Transceivers with internal AC-termination +3V3 TD+ TD- Place level translators as close to netX pins as possible! Hi-Speed single ended signals. Keep traces as short as possible! BIAS resistors. Place as close to level translators as possible! Keep traces as short as possible! TX RX SD RD+ RD- Termination resistors. Place as close to level translators as possible! Differential signal lines, Zdiff = 100 Ohm + TXD+ (IN) - TXD - (IN) + RXD+ (OUT) - RXD - (OUT) + SD FX Transceiver - Single ended signal line, Z = 50 Ohm netX Termination resistors. Place as close to level translators as possible! +3V3 SD+ - Figure 77: netX Ethernet Circuit (Fiber Optic), Component Placement with AC-Termination Note: 4.10.2.4 Please also consider the routing hints for differential signal lines in chapter 4.2.6, which correspondingly also apply to the Fiber optic interface! Diagnostic Monitoring Interface For netX fiber optic designs that are to be used with Real-time Ethernet protocols, especially PROFINET, the fiber optic transceivers must be equipped with DMI (Digital Diagnostics Monitoring Interface), providing status information, like the AFBR-5978Z or QFBR-5978AZ from Avago Technologies. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 111/158 While I²C components can usually be connected to a common signal bus as they can normally be individually addressed through their I²C device address, this is unfortunately not possible with the AFBR-5978Z/QFBR-5978AZ, since these devices do not provide a hardware configurable device address. Each AFBR-5978Z/QFBR-5978AZ uses the same device address, which allows coexistence with other I²C components (sensors, memories, etc.) but not with a second AFBR5978Z/QFBR-5978AZ Since Real-time Ethernet protocols usually require two Ethernet channels and hence also two Transceivers, solution for the addressing problem had to be found and is described below. With netX100/500, an external component is required to switch the SDA signal line of the netX I²C controller between the transceiver interfaces, while they again share the same SCL signal line. Since the SDA is a bi-directional signal, the use of an integrated analog switch is the easiest solution. As the I²C interface of the netX100/500 uses dedicated signal pins, they could be equipped with appropriate internal pull-up resistors (5 kΩ), which basically makes external signal pull-ups obsolete, however two week pull-ups (47 kΩ) are still required to avoid floating of the currently disconnected transceiver SDA signal. The schematic below also shows the secure EEPROM (holding license information and MAC addresses), connected to the same I²C bus, which is no problem, since I²C components of different type or model usually have different device addresses, which is also the case here. This solution has been tested with a MAX325 analog switch, however any analog integrated switch with similar (or better) characteristics (Rdson, pin capacitance, bandwidth) may be used. The following figure shows the schematic for netX100/500: AT88SC0104C +3.3V 1 2 3 VCC NC NC NC SCL GND SDA +3V3 7 6 GND 5 GND I2C_SCL I2C_SDA 47k NC 47k 4 8 Channel 0 SCL SDA W15 W14 MAX325 * +3V3 1 8 2 7 3 6 RD RDn TD FX TDn Transceiver SD 4 5 (QFBR 5978Z) Channel 1 SCL SDA PIO07 netX500/100 RD R17 RDn * Some alternative parts: - ADG723 (Analog Devices) - DG9434 (Vishay) - MAX4643 (Maxim) TD TDn FX Transceiver SD (QFBR 5978Z) Figure 78: netX100/500 I2C Interface Fiber Optic Transceivers netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 112/158 Software considerations netX100/500 With netX100/500, the level of PIO07 must be set accordingly before accessing the desired transceiver. When PIO07 is set to Output mode and low level, the analog switch will connect the netX I²C SDA signal to the SDA signal of Transceiver 0, while setting PIO07 to Output mode and high level, will let the switch connect the SDA signal to Transceiver 1. The PIO signals PIO00 to PIO31 are controlled by the PIO_OUT and PIO_OUT_EN registers, please refer to the netX100/500 Program Reference Guide for details. Note: Please note, that the information above is only relevant when accessing the diagnostic interfaces of the Transceivers without using Hilscher firmware or stacks, since the appropriate functionality and the diagnostic interface communication routines will be integrated in any appropriate software from Hilscher. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.10.3 113/158 Ethernet PHYs unused If the internal Ethernet PHYs are not used in a netX design, the signal pins (RXP/RXN, TXP/TXN) should simply be left open. However, all power supply pins must still be connected, as well as the reference resistor, as shown on the following schematics: + 1.5V F17 PHY_VDDCAP H17 PHY0_VDDCART D20 PHY1_VDDCART C2 10µ J20 PHY_VDDIOAT F18 PHY_VDDIOAC PHY0_TXP PHY0_TXN PHY0_RXP PHY0_RXN PHY1_TXP PHY1_TXN PHY1_RXP PHY1_RXN PHY_EXTRES netX100 netX500 PHY_ATP C4 10µ GND G21 G20 H21 H20 F20 F21 E20 E21 G19 G17 R23 12.4k PHY_VSSAT PHY_VSSACP PHY0_VSSAR PHY0_VSSAT1 PHY0_VSSAT2 PHY1_VSSAR PHY1_VSSAT1 PHY1_VSSAT2 J21 E18 H18 H19 G18 D19 E19 F19 + 3.3V GND Figure 79: netX100/500 Ethernet Circuit (PHYs Not Used) netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.10.4 114/158 Ethernet Status LEDs Each of the netX Ethernet ports provides two status LED signals: Link and Activity. The link status LED is lit, when a link has been established on the corresponding Ethernet port, while the yellow activity LED flickers when data is received or transmitted on the corresponding port. The following table shows the standard pin assignment for the status LEDs Function LED color Pin name an number Ethernet Port 0, Link Sat. green XM0_IO0 N19 Ethernet Port 0, Activity yellow XM0_IO1 N18 Ethernet Port 1, Link Sat. green XM1_IO0 P19 Ethernet Port 1, Activity yellow XM1_IO1 P18 Table 36: Status LEDs for Ethernet Ports netX100/500 use the IO signals of XMAC0 and XMAC1 for Ethernet status signaling. The schematics below must be used whenever the design is to be operated with loadable Firmware from Hilscher. + 3.3V Link Act. g y g y XM0_TX XM0_RX XM0_IO0 XM0_IO1 XM1_TX XM1_RX netX100 netX500 XM1_IO0 XM1_IO1 Rv Act. Rv Link Rv Channel 1 Rv Channel 0 N20 N21 N19 N18 P20 P21 P19 P18 Figure 80: netX100/500 Ethernet Status LED Circuit netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.10.5 115/158 Real Time Ethernet Besides running standard Ethernet protocols, the netX is able to run all current Real Time Ethernet (RTE) protocols. The physical interface for RTE protocols is identical to the standard Ethernet port as described in the preceding chapters, except some additional synchronization signals that may be required depending on protocol and application as well as some additional status LED signals. Both are described in the following chapters. Note: Regardless if these signals are used in an application, any RTE protocol will always occupy the XPEC3/XMAC3 unit on the netX100/500, hence this unit can never be used for any other purpose like a field bus interface, whenever an RTE protocol is running. 4.10.5.1 Sync signals The netX100/500 provides up to two additional I/O signals for these purposes, which are generally connected through the XM3_IO0 and XM3_IO1 pins (XMAC3 I/O pins). The following table lists the different protocols and the additional signals: RTE protocol Master/Slave XMAC3 signal Pin Function Type Remarks SERCOS III Device XM3_IO0 U19 CON_CLK Out Configurable XM3_IO1 U18 DIV_CLK Out Configurable XM3_IO0 U19 CYC_CLK CON_CLK In/Out Configurable XM3_IO1 U18 DIV_CLK XM3_IO0 U19 Sync 0 Out XM3_IO1 U18 Sync 1 Out XM3_IO0 U19 IO_Output Out Trigger for Outputs valid, also used for certification (start of red phase) XM3_IO1 U18 IO_Input Out Trigger for sample inputs XM3_IO0 U19 SoC Out configurable, “Start of Cycle” received event XM3_IO1 U18 - Master EtherCAT PROFINET IRT Ethernet Powerlink Slave Controller/Device Controlled Node Table 37: Additional RTE Sync Signals netX100/500 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.10.5.2 116/158 RTE Status LEDs In Addition to the standard Ethernet Status LEDs (Link Status and Activity), up to four further LEDs (two dual LEDs) have been defined by the different RTE Protocols. The signals used for driving these LEDs (PIO0-3) are identical with the signals used for Field bus status LEDs on XMAC0 and XMAC1 (see also chapter 2.1.3 for pinning details), which however is not really a conflict, since RTE applications usually require both Ethernet ports and a field bus stack can not run on XMAC0 or XMAC1 when these XMACs are already used by an Ethernet application. Firmware Label Dual LED COM 0 SF EtherCAT RUN Powerlink BS PIO2 red PIO3 red BF green red ERR green red BE SERCOS III STA Master SERCOS III S3 Slave EtherNet/IP MS green red ERR Open Modbus/TCP RUN green red ERR VARAN RUN green red ERR green red green Meaning COM 1 PIO0 PIO1 PROFINET Label - red green red NS SF: System Failure BF: Bus Failure RUN: Run ERR: Error BS: Bus Status BE: Bus Error STA: Status (Phase) ERR: Error S3: orange = red and green at the same time. MS: Module Status NS: Network Status RUN: Run ERR: Error RUN: Run ERR: Error Table 38: Status LEDs for Real Time Ethernet Applications All RTE Status LED I/Os are defined as active low. The following schematic shows, how to connect the LEDs. + 3.3V PIO0 PIO1 PIO2 PIO3 g Rv r Rv Rv g COM1 r Rv COM0 M21 M20 M19 M18 netX100 netX500 Figure 81: netX RTE Status LED Schematic netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 117/158 The appropriate value for Rv depends on type and color of the LED (standard value = 270 Ω). Use either two red/green Dual-LEDs or two pairs of single LEDs with the LEDs of each pair placed close to each other for the COM0 and COM1 indicators. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 118/158 4.11 Fieldbus Interface The netX controllers are equipped with flexible communication processors (xPEC/xMAC units, also referred to as XC units) that allow to realize virtually any field bus interface on the market, by simply adding the appropriate physical layer circuit. While the netX500 provides a total of four XC units, the netX100 has three XC units and an additional unit with limited functionality (used for Real-time Ethernet protocols). The standard XC port for a single channel field bus application on the netX100/500 is xMAC2, as this still allows using the Ethernet interface on XC0 and XC1. xMAC3 is generally not available for field bus interfaces on the netX100 and can further not be used for field bus interfaces on the netX500 when running a Real-time Ethernet protocol! All common field bus interfaces are serial interfaces with a Transmit and Receive signal, while some of them use an additional control signal or status signal, hence the xMAC units that directly connect to the field bus physical layer circuit provide an XMi_TX, an XMi_RX and two I/O signals (XMi_IO0 and XMi_IO1), whereas currently only one of them is used by current field bus interfaces. Each XC unit also provides a clock input/output signal (XMi_ECLK) that either allows synchronizing external hardware to the XC clock or feeding an external clock to the XC unit. Both options are currently not used. The pinning of the XMAC signals is fixed for netX100/500. For that reason it is strongly recommended to adopt the proposed MMIO assignment for the XMAC signals as shown in the following example schematic. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits XM2_TX XM2_RX XM2_IO0 XM2_IO1 119/158 R20 R21 R19 R18 - PROFIBUS-DP - CANopen - DeviceNet - ASi CTRL - CC-Link - CompoNet Fieldbus Physical Layer Interface XM0/1_TX XM0/1_RX XM0/1_IO0 netX 100 XM0/1_IO1 XM2_TX XM2_RX XM2_IO0 XM2_IO1 R20 R21 R19 R18 - PROFIBUS-DP - CANopen - DeviceNet - ASi CTRL - CC-Link - CompoNet Fieldbus Physical Layer Interface XM0/1/3_TX XM0/1/3_RX XM0/1/3_IO0 netX 500 XM0/1/3_IO1 Figure 82: netX100/500 Fieldbus Interface netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.11.1 120/158 AS interface Master As there are no pure ASi transceivers on the market and generating the sin² signals is not trivial, an ASi interface with the netX still requires the use of an appropriate ASi-ASIC (→ ZMD). The following simplified example schematic shows the physical layer circuit for a netX AS-interface, still using the discontinued A2SI chip which is replaced by the ASI4U. More detailed schematics can be found in the Reference Section in Chapter 5. For details, consult A2SI data sheet A2SI (Master Mode) +3.3V XMi_TX XMi_RX VDD 100k ADuM1301 VDD 10k +5V ASI_TX ASI_RX USR UOUT UIN TXD +ASi RXD -ASi 1 2 Asi+ Asi- 0V XMi_IO0 netX ASI_PF Powerfail GND GND + Umin GND Figure 83: Basic Circuit for netX AS-Interface netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.11.2 121/158 CANopen Interface A CANopen interface can be implemented as shown in the following schematics. More detailed schematics (pin numbers) can be found in the in the Reference Section in Chapter 5. +3.3V VCC XMi_TX CO_TX 390 HCPL0601 PCA82C251 VCC TX H RX L REF RS GND & 220 GND 7 2 CAN_H CAN_L HCPL060L 390 XMi_RX netX VCC CO_RX SUB-D, 9-pin, male & 390 GND 3.3V 5V 3 DGND GND Figure 84: Basic Circuit of netX CANopen Interface netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.11.3 122/158 CC-Link Interface A CC-Link interface can be implemented as shown in the following schematics, which are based on the reference schematics from the CC-Link specification. The purpose of the AND gate in the RX signal is simply to convert the 5V signaling voltage from the photo coupler to 3.3V level. More detailed schematics (pin numbers) can be found in the in the Reference Section in Chapter 5. +5V_ISO VCC XMi_IO0 CCL_SDG 1k HCPL0601 220 & 1 GND 75ALS181 HCPL-0720 VCC XMi_TX 47k +5V VCC VCC CCL_TX 1 GND ZCYS51RS-M3PAT GND 1 680 GND XMi_RX 10k CCL_RX VCC VCC & 680 47k HCPL-0720 1 netX GND 2 DA DB RD6.2Z 3 5 DG GND For Details refer to the CC-Link specification 3.3V 3,3n / 50V 4 3.3V 5 5V SLD FG GND_ISO GND PE Figure 85: Basic Circuit for netX CC-Link Interface netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.11.4 123/158 CompoNet Interface A CompoNet interface can be implemented as shown in the following schematics, which are based on the reference schematics from the CompoNet specification. The purpose of the AND gate in the RX signal is simply to convert the 5V signaling voltage from the AD51/025 to 3.3V level. More detailed schematics (pin numbers) can be found in the in the Reference Section in Chapter 5. +5V AD51/025 VDD XMi_RX CP_RX MMZ1608B301C 10 & 03-7104 10 XW7D-PB4-R BS+ 150 BDH CP_TX 10 XMi_IO0 10 BS- ACM3225-102-2P GND CP_EN RD6.2SB1 RD6.2SB1 1k 220p netX BDL MMZ1608B301C RD6.2SB1 220p 15 XMi_TX RD6.2SB1 GND Figure 86: Basic Circuit for netX CompoNet Interface netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.11.5 124/158 DeviceNet Interface A DeviceNet interface can be implemented according to the following simplified schematics. More detailed schematics can be found in the in the Reference Section in Chapter 5. +3.3V VCC XMi_TX DN_TX 470 HCPL0601 PCA82C251 VCC TX H RX L REF RS GND & 270 GND 4 2 CAN_H CAN_L PESD1CAN HCPL060L VCC 1,3K XMi_RX netX XMi_IO0 DN_RX DN_PF & 470 GND Powerfail For Details refer to the DeviceNet specification from the ODVA TLP281 5 4,3K V+ 1,3K 4,02K U 3.3V 1 5V 3 VDRAIN GND 1M 1M 15 n/1kV 15 n/1kV PE Figure 87: Basic Circuit for netX DeviceNet Interface netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.11.6 125/158 PROFIBUS Interface A PROFIBUS interface can be implemented according to the following simplified schematics. More detailed schematics can be found in the in the Reference Section in Chapter 5. Note: The (isolated) 3.3V to 5V DC-DC converter should either be a regulated model or should be equipped with an appropriate downstream LDO regulator. Otherwise, the secondary voltage may be too high, resulting in out-of-spec signal levels on the PROFIBUS line! +3.3V 6 IL3585E VCC XMi_RX netX 330 4 CNTR-P 100k XMi_TX VCC PB_ENB PB_TX 3 8 PB_RX GND GND 100k XMi_IO0 VP RXD/TXD-P RXD/TXD-N SUB-D, 9-pin, male 3.3V 5 5V GND 1M (regulated!) DGND 2.2 n/1kV Shield1 Shield2 PE Figure 88: Basic Circuit for netX PROFIBUS Interface netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.11.7 126/158 Fieldbus Status LEDs For each of the up to 4 possible Field bus ports, two1) status LED signals are defined, which function depends on the type of Field bus interface. Function Pin name and number netX100/500 Field bus 0, COM0 PIO0 M21 Field bus 0, COM1 PIO1 M20 Field bus 1, COM0 PIO2 M19 Field bus 1, COM1 PIO3 M18 Field bus 2, COM0 PIO4 M17 Field bus 2, COM1 PIO5 N17 Field bus 3, COM0 Note 2) PIO6 P17 Field bus 3, COM1 Note 2) PIO7 R17 Table 39: Status LEDs for Fieldbus Ports Fieldbus Protocol LED Name LED Color PROFIBUS-DP Master and Slave COM green red CANopen Master and Slave CAN green red DeviceNet Master and Slave MNS green red AS-Interface Master COM green red L RUN/L ERR green red Two LEDs required by spec: MS and NS green red CC-Link Slave 1) CompoNet Master and Slave Table 40: Fieldbus Status LED Colors Note: 1) CompoNet requires four status LED signals 2) Field bus 3 is generally not available on netX100 and also not on netX500 when running RTE applications, requiring hardware synchronization! netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 127/158 4.12 A/D Converter When using the AD converters of the netX100/500, the supply voltages for the ADC circuit and its reference voltages should be filtered to avoid power supply noise to influence accuracy of the sampled values. The following circuit shows a recommendation, however the filter components may have to be modified, to meet the special requirements of a particular system. Note: All filter components are application specific and should be evaluated. Shown values are only an example! AA5 ADC0_IN0 Y5 ADC0_IN1 W5 ADC0_IN2 V5 ADC0_IN3 ADC0_VDDIO ADC0_IN0 ADC0_IN1 ADC0_IN2 ADC0_IN3 3.3V W6 1k Ferrit 1000 OHM @ 100 MHz, 200 mA ADC_IO ADC0_VREFP V6 ADC_VREFP + ADC0_VREFM ADC0_VSS AA4 100 nF Y4 10 µF Filtered supply for additional analog circuits ADC_AGND Optional filter for separate analog ground GND ADC1_IN0 ADC1_IN1 ADC1_IN2 ADC1_IN3 ADC1_VDDIO ADC1_VREFP ADC1_VREFM ADC1_VSS Y3 W3 V4 U5 ADC1_IN0 ADC1_IN1 ADC1_IN2 ADC1_IN3 W4 AA3 V3 U4 netX100/500 Figure 89: ADC Circuit netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 128/158 If the second ADC-channel is not used, it still needs to powered, as shown in the following schematic: AA5 ADC0_IN0 Y5 ADC0_IN1 W5 ADC0_IN2 V5 ADC0_IN3 ADC0_VDDIO ADC0_IN0 ADC0_IN1 ADC0_IN2 ADC0_IN3 3.3V W6 1k Ferrit 1000 OHM @ 100 MHz, 200 mA ADC_IO ADC0_VREFP V6 ADC_VREFP + ADC0_VREFM ADC0_VSS 100 nF AA4 Y4 10 µF Filtered supply for additional analog circuits ADC_AGND Optional filter for separate analog ground GND ADC1_IN0 ADC1_IN1 ADC1_IN2 ADC1_IN3 ADC1_VDDIO ADC1_VREFP ADC1_VREFM ADC1_VSS Y3 W3 V4 U5 3.3V W4 AA3 V3 U4 GND netX100/500 Figure 90: ADC Circuit, One Channel Used netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 129/158 If the ADCs are nit used, they still need to be powered, as shown in the following schematic: 3.3V AA5 ADC0_IN0 Y5 ADC0_IN1 W5 ADC0_IN2 V5 ADC0_IN3 ADC0_VDDIO ADC0_VREFP ADC0_VREFM ADC0_VSS ADC1_IN0 ADC1_IN1 ADC1_IN2 ADC1_IN3 ADC1_VDDIO ADC1_VREFP ADC1_VREFM ADC1_VSS W6 V6 AA4 Y4 Y3 W3 V4 U5 W4 AA3 V3 U4 GND netX100/500 Figure 91: ADC Circuit, ADCs Unused netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 130/158 4.13 PWM Interface The netX100/500 is equipped with two independent PWM units, each with a three phase complementary output (e.g. for controlling electric motors) and an additional single phase output for supplying resolver units. Due to the necessarily limited pin resources of the netX controllers, the use of pin sharing was inevitable, which implies some restrictions regarding the parallel use of certain chip resources. The following picture roughly shows the dependencies and restrictions that may come into play when using the PWM and/or Encoder interface and communication channels: XPEC0 XPEC1 XPEC2 XPEC3 XMAC0 XMAC1 XMAC2 XMAC3 PWM0 (PWM2) PWM1a/b (PWM3a/b) ADC A B Fiberoptic PHY 1 Fiberoptic PHY 0 Encoder 0/1 PIO 0-7 PIO Pins XM0 Pins XM1 Pins XMAC ECLK 0/1/2/3 XM3 Pins Figure 92: PWM/Encoder/xMAC/xPAC Resource Sharing The picture shows the following major restrictions: Designs that also make use of the encoder interface can only use unit PWM1. Since using PWM1 rules out the use of xMAC3 (which must be disabled when controlling these units from the ARM netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 131/158 CPU), Real Time Ethernet designs with Encoder and PWM interface are not possible (or would require customized xMAC code, that can only be created by Hilscher (custom development)). When using unit PWM0, xMAC2 must be disabled (allowing this unit to be controlled by the ARM CPU), which excludes the use of a field bus protocol on xMAC2 or would again require customized xMAC code. Further, using PWM0 or Encoder interface blocks PIO0-7 which are the standard resources for RTE and field bus status LEDs. In that case, other I/O resources must be used for the LEDs. The external circuit for PWM applications strongly depends on the application, hence examples are not provided here. The appropriate pins for the signals of the PWM units which are PWM0E_U, Un, V, Vn, W, Wn, RSV (for Resolver) and FAILn for unit PWM0 and which are PWM1 A_U, Un, V, Vn, W, Wn, RSV and FAILn for unit PWM1, pinning option A and PWM1B_U, Un, V, Vn, W, Wn, RSV and FAILn for pinning option B, can be found in the corresponding pin table in Chapter 7.6 (Pin Table sorted by signals) of the netX100/500 Technical Data Reference Guide. Note: The following popular pitfall with netX PWM designs must be avoided: Both PWM units are equipped with an active low Failure Signal input that immediately stops the corresponding unit and sets all outputs low when active. These signals are PWM0E_FAILn (pin P17, shared w. PIO06) for PWM unit 0 and PWM1 A_FAILn (pin N18, shared with XM0_IO1) for PWM unit 1, pinning option A or PWM1B_FAILn (pin T20, shared with XM2_ECLK) for pinning option B. Since all these pins are equipped with internal pull-down resistors, the failure signals are always active when unconnected. Hence on any netX PWM design that does not make use of a failure signal, the appropriate signal must be pulled high by an external pull-up resistor, otherwise the corresponding PWM unit will not operate! Please also note, that the FAILn signals are not 5 V tolerant, hence 3.3 V levels may only be used here! netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 132/158 4.14 Encoder Interface The netX100/500 provides an Encoder unit allowing to connect two separate incremental rotary encoders (quadrature encoders), used for capturing position (angle), speed and direction of a rotating axle (mostly used with motion control applications). As it can be seen on the picture in the previous chapter, using the Encoder unit rules out the parallel use of PWM unit 0 and also blocks PIO0-2 and/or PIO3-5 and PIO6-7 , which are the standard resources for RTE and field bus status LEDs. In that case, other I/O resources must be used for the LEDs. However, since the pinning option for the Encoder unit allows enabling encoder 0 and encoder 1 and the two optional MP signals individually, the parallel use of a single encoder and up to 5 PIO signals is possible. Using the encoder also requires XMAC2 to be disabled (allowing the encoder unit to be controlled by the ARM CPU), which excludes the use of a field bus protocol on XMAC2 (or which would require customized XMAC code, that can only be created by Hilscher (custom development)). Each encoder interface provides three signal inputs named A, B and N. A and B are the two quadrature signals, while N is the index signal, indicating position 0 of the rotary encoder. There are two additional optional input signals named MP0 and MP1 that can be used for initiating the storage of the current position or system time to up to four different capture registers. As all encoder signal inputs expect single ended digital signals with 3.3 V level, only appropriate encoders may be connected directly to the inputs. When using encoders with differential outputs and/or 5 V signaling levels, appropriate line receivers and/or level shifters must be connected between encoder and netX. The following schematics show an example (only one encoder and only one signal shown in detail) of a possible circuit: +5V 16 M21 A 1 1 2 PIO1 / ENC0_B PIO2 / ENC0_N M20 M19 B N 3 74LCX04 + - GND PIO4 / ENC1_B PIO5 / ENC1_N PIO6 / ENC_MP0 PIO7 / ENC_MP1 netX 100/500 5 A An 7 0.1µF 4 75115 PIO3 / ENC1_A Rotary Encoder & 120 PIO0 / ENC0_A +5V 560 +5V Vcc capacitors are not shown in this schematic 560 +3.3V 8 M18 2.2nF M17 GND Identical circuit as above B Bn Identical circuit as above N Nn N17 P17 R17 Application specific use Figure 93: Encoder Circuit Example netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits Note: 133/158 Designers should note, that the shown schematics are just an example and that the best circuit for their application may be different. Unless designers have appropriate experience with encoder circuitry, we strongly recommend to contact the manufacturer of their encoders to find the best solution for their design. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 134/158 4.15 LCD Interface The netX500 is equipped with an LCD controller, allowing to connect color/bw STN or DSTN as well as TFT displays. Connecting a display does usually not require any additional components and is accomplished by simply hooking up the display signals to the appropriate LCD signals of the netX500. Depending on the display type (and the corresponding register settings of the LCD controller), the LCD data lines LCD_D[17:0] have different mappings. Please consult the netX100/500 Technical Data Reference Guide (chapter 2.24) for a table listing all possible display modes and the corresponding data signal mapping. Chapter 7.4 (“Signal Definitions”) lists the 5 control signals of the LCD controller and their functionality in STN and TFT display mode. Besides the designated LCD display signals another signal may be required for controlling the backlight of the connected display. For this purpose, GPIO14 has been assigned an appropriate standard function. It can be simply set or cleared in order to turn on and off the display backlight, or, if supported by the display, switched to PWM mode to control the intensity of the backlight. If the display can’t handle the PWM signal directly but requires a constant voltage for intensity control, an RC filter as shown below must be implemented. Note: Please note, that this functionality has only been realized with Windows CE images for netX500 boards. Further, the GPIOs are in no way linked to or controlled by the LCD controller, hence the backlight control functionality must always be realized completely by software! GPIO14 10k 10k 100nF Backlight 100nF netX 500 GND GND Figure 94: LCD-Backlight-PWM; RC-Filter; Windows CE netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 135/158 4.16 Touch Panel Interface Though the netX500 is not equipped with a touch panel controller, such a functionality can easily be implemented by using two I/O signals and two channels of the internal AD converter, along with a few external components, as shown in the following schematic: TP-YON U18 TP-XON U19 XM3_IO1 XM3_IO0 +3.3V 16 4 1 Y3 2 100nF W3 3 V4 1k YU U5 5 XR AD1_IN2 AD1_IN3 47nF 220k 6 AD1_IN1 7 NLAS44599 12 YL GND +3.3V 9 10 100nF 220k XL 4-wire Resistive Touchpanel AD1_IN0 11 1k 13 47nF 14 8 GND netX 500 15 GND Figure 95: Touch Panel Circuit The NLAS44599 (ON Semiconductor) is an integrated component containing 4 analog switches, perfectly meeting the requirements of this application. However, other analog switches or four single FETs may be used as well. The purpose of the diodes (e.g. BAR43S) is to protect the netX analog inputs from possible damage caused by ESD (as it lies in the nature of touch panels, that they are being touched by human hands, they are always subject to electrostatic discharge). The RC-filter comprising of the 1k resistor and the 47nF capacitor is just an example and may need to be adapted to the requirements of your design. The resources (AD converter channels and I/Os) shown above, must also be chosen, when users want to run Windows CE images provided by Hilscher, already containing an appropriate touch panel driver. When other operating systems (e.g. rcX) are used, users need to program their own driver and may then want to select other I/O signals than the XM3 I/Os (as this would rule out the use of RTE protocols), while the ADC channels may then also be freely selected. Please note, that the above schematics do not show the (always necessary) power supply of the AD converter. See chapter 4.12 (A/D Converter) for an example how to connect the ADC power supply pins. The filtered 3.3 V voltage from the ADC power supply circuit should also be used for the +3.3 V shown in the schematics above. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 136/158 To make the circuit and the netX work as a touch panel controller, appropriate driver software must perform the following tasks: Starting in idle mode, the two I/O signals (XM3_IO0 and IO1) must be held low and the analog value on the two ADC inputs must be captured periodically. In this state, all switches are turned off and due to the 200k pull-up and pull-down resistors, the value on the YU input will be around maximum, while the value on the XR input will be around 0, as long as the panel is not being touched. In this case the application is to remain in idle mode. If the XR input value is significantly higher than 0 and the YU input value significantly lower than max., it can be assumed, that the panel is currently being touched. Now the TP-XON must be set to high level, which turns on the two upper switches, connecting XR to 3.3 V and XL to GND. At the position being touched, the conducting XL-XR and YL-YU layers of the panel contact each other, building a voltage divider with the voltage at the touch point being proportional to the X position of the touched point. After a (panel specific) settling time, this voltage (and hence the corresponding position) can be measured at the YU input. When the X position has been captured, the TP-XON I/O (XM3_IO0) must be set to low level again, while the TP-YON I/O (XM3_IO1) must set to high level. This turns on the two lower switches, connecting YU to 3.3 V and YL to GND. Now (again after a certain settling time) the voltage level at the XR input resembles the Y position of the current touch point. When the Y position has been captured, TP-YON I/O (XM3_IO1) must be set to low level again. Now the current position is known and the system can return to idle mode. Due to non-linearity and wear/aging, it is recommended, to also implement a calibration function that shows a few calibration points at known positions on the display, while the user consecutively touches these points. By comparing the measured coordinates to the coordinates of the calibration points, appropriate correction factors can then be calculated, allowing to compensate the deviations. The required settling time between changing the switch signals and performing the acquisition of the analog touch panel signals must be evaluated. In electrically noisy environments it may also be necessary to perform several measurements and use the average, trading response time for accuracy. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 137/158 4.17 PIO The netX chip contains several programmable input/output lines. Each of the 83 PIO can be used as simple input or output without any additional features. The first 31 PIO pins (PIO0-PIO30) are shared with Motion Control pins, LCD pins and ETM pins. The 53 other Pins (PIO32-PIO84) are shared with Host Interface Pins. (PIO31 does not exist). PIOs 0 – 7 usually drive Fieldbus and RT Ethernet status LEDs in standard applications. PIO 0 – 30 The PIO 0 – 30 pins are equipped with 50 kΩ pull up resistors with a minimum resistor value of 20.6 kΩ and maximum resistor value of 116.4 kΩ. The maximum input/output current is 6mA. PIO 32 – 84 The PIO 32 - 84 pins are not equipped with pull-up or pull-down resistors. The maximum input/output current is 18 mA. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 138/158 4.18 Power Supply netX100 and netX500 both require an I/O voltage supply of 3.3 V and a core voltage supply of 1.5 V. For worst case scenarios, the 3.3 V supply should be able to source a current of 400mA for the netX part (netX, memory, etc.) of the circuit. When the core voltage regulator is also supplied by the 3.3 V rail, the max. current of course increases accordingly. The core supply should be able to deliver 1 A. For certain applications (e.g. applications that do not use the Ethernet ports) lower max. currents may be sufficient, however in that case, the corresponding Technical Data Reference Manual of the netX chip should be considered for details about power consumption. It is recommended to implement a separate core voltage supply for the netX, even if a 1.5V supply is required by other parts of the system (e.g. FPGA). The output voltage of this separate supply should be “programmable” (either by appr. digital input pins or by external resistors. This allows to continue to use the same design when the used netX type has gone through a die shrink process, which always results in a reduced core voltage. 4.18.1 Core Voltage Regulator A Hilscher standard circuit for the core voltage regulator uses a FAN2001 (Fairchild Semiconductor) step-down DC-DC converter and is shown below: +3V3 +1V5 (2.5V - 5.5V) SW 6 3.3µH 1.18A FB 4 2 PGND AGND 7 22uF 1.96k 22uF FAN 2001 GND GND 1.8k 1 Vin 5 NC 3 EN GND GND GND Figure 96: netX Core Voltage Regulator The complete part name is FAN2001MPX, the inductor is a CR32NP-3R3 (Sumida), and the capacitors are ceramic types (X5R), resistors 1%. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 4.18.2 139/158 Alternative Core Voltage Regulator An alternative part, especially for designs with space constraints, is the EN5312Q (Enpirion), which delivers 1A, has an integrated inductor and provides 3 digital inputs for setting the output voltage, requiring only two 10 µF ceramic caps as additional external components (see www.enpirion.com for detailed information). +3V3 1 VIN1 2 VIN2 1 0805 +1V5 T101 5 VOUT1 6 VOUT2 7 VOUT3 20 ENABLE 19 15 VS0 VSENSE 18 16 VS1 VFB 17 VS2 3 GND1 21 4 AGND GND2 C101 10uF 2 1 0805 C102 10uF 2 EN5312Q GND Figure 97: Alternative Core Voltage Regulator 4.18.3 Common Supply Voltage Regulator 3.3 V A standard circuit for a common supply voltage of 24V, which operates from 9V to 30V and delivers 3A at 3.3V, is shown in the following schematic: T100 1 2 5 6 D1 6 VIN 2 EN/UVLO K101 D2 D3 C104 1 0805 100nF FDC5612 D4 R103 BST VSW C100 1 C101 1 C102 1210 10uF 1210 10uF 2 2 2 0603 1 2 1 2 5 6 K100 5 6 LDS CSH G S 1 MIC2198 13 9 STEPDOWN-MIC2198YML 1 PMEG4005 10uH GND 4 R105 3 2 C106 3 1 1206 5 2 1 2.2k GND 4 0603 100nF FB GND C107 2 2 1 R104 3 4 0805 10uF 1 2 PMEG4005 6 5 S 3 1 4 8 2 1210 10uF 100nF 2 D1 D2 D3 FDC5612 D4 VOUT GND1 C105 0805 11 C103 R100 1 10 0603 2.2nF 1 G 4 0603 1 COMP 3 12 HSD 7 VDD R106 0.018 +3V3 R101 4.7k 2 2 1 0603 1 9V-24V Synchronous Buck Controller 2 R102 1.5k 1 C108 1 C109 0805 22uF 0805 22uF 2 2 2 GND Figure 98: netX +3V3 Supply netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Standard Circuits 140/158 This circuit provides high efficiency over the complete input voltage range, due to the synchronous switching, consumes appr. 320 mm2 board space and costs appr. 3.50 €. 4.18.4 Voltage Regulator 5 V The same circuit with 6,8kΩ for R101 and 1,3kΩ for R102 delivers 5V. T100 1 2 5 6 D1 6 VIN 2 EN/UVLO K101 D2 D3 C104 1 0805 100nF FDC5612 D4 R103 BST VSW C100 1 C101 1 C102 1210 10uF 1210 10uF 2 2 2 0603 1 2 1 2 5 6 K100 5 6 LDS CSH G S 1 MIC2198 13 9 STEPDOWN-MIC2198YML 1 PMEG4005 10uH GND 4 R105 3 2 C106 3 1 1206 5 2 1 2.2k GND 4 0603 100nF FB GND C107 2 2 1 R104 3 4 0805 10uF 1 2 PMEG4005 6 5 S 3 1 4 8 2 1210 10uF 100nF 2 D1 D2 D3 FDC5612 D4 VOUT GND1 C105 0805 11 C103 R100 1 10 0603 2.2nF 1 G 4 0603 1 COMP 3 12 HSD 7 VDD R106 0.018 +5V R101 6.8k 2 2 1 0603 1 9V-24V Synchronous Buck Controller 2 R102 1.3k 1 C108 1 C109 0805 22uF 0805 22uF 2 2 2 GND Figure 99: netX +5V Supply netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 General Design Considerations 5 141/158 General Design Considerations 5.1 5.1.1 Thermal Behavior Basics Since netX100/500 designs are often used in industrial environments, fitness for high temperature ranges is frequently an issue. Depending on the used interfaces and chip type, netX100/500 designs can have a power dissipation from typically 1.1 W (PHYs for Ethernet turned off) up to 1.6 W (integrated PHYs in use), which results in appropriate warming of the netX silicon. While there is a hard limit for the chip’s junction temperature at 125 °C above which malfunction and permanent damage may occur, it is always desired to keep the junction temperature as low as possible, as a semiconductor’s statistical life time generally decreases with rising temperature. Since additional power dissipation that is being avoided in the first place does not result in additional heat that needs to be dissipated, hardware designers should make sure, that all netX power supply circuits deliver nominal voltage levels (3.3 V I/O and 1.5 V core) and do not make use of the possible headroom (3.6 V I/O and 1.65 V core). The BGA packages used with all current netX chips have mainly two paths of heat dissipation, which are the path through the package balls into the copper of the PCB (mainly power and ground planes) and the path from the chip surface (top) to the environment. The resulting thermal resistance of the first path strongly depends on the characteristics of the PCB, which also makes the thermal behavior of a design strongly dependant on the PCB. The only possibility to decrease the influence of the PCB is to use a heat sink, which can considerably reduce the thermal resistance of the second heat dissipation path and also improves the overall thermal behavior of the design. 5.1.2 Estimates The Technical Data Reference Guides (chapter “Thermal package specification”) of the netX chips provide the following formula that allows calculation of the chip junction temperature ( T j ) at a given environment temperature ( Ta ), power ( PnetX ) and thermal resistance ( Rth ) of the heat sink: T j = Ta + (θ jc + Rth ) × PnetX The chip specific value of θ ic can be found in the above mentioned chapter of the appropriate Technical Data Reference Guide. Please note, that the formula above only allows an estimate for the possible junction temperature of a particular design, as there is still an influence of the PCB characteristics. The parameters have been evaluated using certain test boards and may hence not be directly applied to a specific design. This applies even more to the second formula, for operation without heat sink! netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 General Design Considerations 142/158 Hilscher netX hardware is usually designed for a maximum junction temperature of appr. 100°C, which is also the recommended value for customer designs. The FIT-rate (FIT = Failure in Time, see appr. chapter of the Technical Data Reference Guide) for the silicon process which netX10/50/100/500 are based on, shows a significant rise in the temperature range between 100°C and the absolute maximum junction temperature, which was the reason for choosing the 100°C. However, since the absolute max. junction temperature is 125°C, it is at a device manufacturer’s discretion if he wants to follow this recommendation or rather decides to accept a higher junction temperature and trade a decrease of the MTBF of his devices for a higher temperature range specification. A major factor of the thermal behavior of a netX design is the size of the PCB. Design experience at Hilscher shows, that designs with a power density of more than 0.15W/cm2 are critical (assuming the 100°C limit for the junction temperature and a maximum ambient temperature of 70°C and considering the common maximum temperatures of peripheral components like SDRAM, FLASH, Reset Generator, etc.), hence the board size should be chosen accordingly. To calculate the power density of a design, simply divide the power dissipation by the area of the PCB. Following there are two examples from the Hilscher netX product line, one that is well within this power density limit and one that is at this limit: Mini PCI Card with Ethernet Dimensions: 44.6 mm x 59.8 mm Area: 26.67 cm² Power consumption: 1.75 W, heat sink, 70°C Power Density: 0.07 W / cm² Figure 100: CIFX 90-RE netIC with Ethernet Dimensions: 21.0 mm x 42.0 mm Area: 8.82 cm² Power consumption: 1.3 W, heat sink, 70°C Power Density 0.15 W / cm² Figure 101: NIC 50-RE netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 General Design Considerations 5.1.3 143/158 Rules of thumb Assuming the recommended 100 °C junction temperature limit, the following rules of thumb can be provided, which are based on Hilscher’s design experience with netX chips: Designs with 45 x 60 mm area and heat sink usually work up to 70 °C. Designs with 45 x 60 mm area without heat sink usually work up to 55 °C. netX500 designs with 30 x 50 mm and heat sink usually work up to 70 °C. When using the internal PHYs, the netX temperature rises by appr. 15 °C. When using the heat sinks, recommended by Hilscher, the maximum temperature of the netX case decreases by approximately. 15 °C. The above rules assume unimpeded convection of the PCB. When a small closed cabinet is used, the maximum ambient temperature (inside the cabinet) must be decreased by approximately 15 °C. When the power density is higher than 0.15 W/cm², it will be critical to make a netX design which operates up to 70 °C. Avoid placing semiconductor components on the bottom side of the PCB within the netX chip area. Resistors or ceramic capacitors may be placed under the netX if they allow operating temperatures up to 100 °C (X7R ceramic). Temperature tests with a netX500 Evaluation board have shown, that it is possible to build designs for extended temperature range (up to +85 °C) with heat sink, resulting in a netX case temperature of ~103 °C (see document “nxdkn-en_Rev3_Waerme.pdf”, available on the Hilscher website). netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 General Design Considerations 5.2 144/158 EMC behavior Designing for EMC is a quite complex issue, already filling countless pages of again countless books and papers and it is not the intention of this document, to further enrich this variety of publications, however a few basic guidelines / hints can be presented, that may be useful for the PCB designer routing a netX design. 5.2.1 Layer Stack Though, depending on the complexity of the design, netX designs using 4-layer PCBs are possible, the use of a 6 Layer board (4 signal layers, one power and one ground plane layer) is recommended. 4 signal layers provide enough space to keep the power and ground planes free from any signal traces and allow shielding areas on top and bottom layers, which contributes to a satisfying EMC behavior of the design. An approved 6-layer stack for netX designs is shown in the following figure: TOP (Components / Routing / Shield) INT3 (Routing) INT1 (Ground) 35 µm CU 100 µm FR4 Prepreg 35 µm CU INT2 (Power) 510 µm FR4 Basematerial INT4 35 µm CU 100 µm FR4 Prepreg 35 µm CU (Routing) BOTTOM (Components / Routing / Shield) 510 µm FR4 Basematerial 35 µm CU 100 µm FR4 Prepreg 35 µm CU Figure 102: Approved netX PCB Layer Stack netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 General Design Considerations 5.2.2 145/158 Decoupling capacitors As with any digital design, the use of a sufficient number of decoupling capacitors is important to provide a stable operation of the design and avoid unnecessary emission. The following picture shows an example how to arrange decoupling capacitors around a netX100/500. +1.5 V +3.3 V +3.3 V +1.5 V +1.5 V +3.3 V +3.3 V +1.5 V Figure 103: netX100/500 Decoupling Caps As the picture already indicates, the power path goes from vias (located as close as possible to the caps) to the caps and from there directly to the netX power pins. However only power pins on the two outer BGA rings should be connected that way. All inner power pins should connect to the plane directly. VDD-CORE VSS VDD-IO VSS VSS VSS VDD-IO VDD-CORE VDD-IO VSS VDD-CORE VDD-IO VDD-IO VSS VDD-IO VDD-IO VSS VDD-IO VDD-CORE VSS VDD-CORE VDD-IO PIN A1 VSS VSS VDD-IO VSS VDD-CORE VSS VDD-IO Figure 104: netX100/500 Decoupling Caps Vias and Inner Plane for VDD-IO and VDD-CORE netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 General Design Considerations 5.2.3 146/158 Power Supply Input Filter When using the 9-30V power supply shown in chapter 3.17, the following filter circuit is recommended, to reduce line based emissions at 500 kHz and harmonics: R4 47 µH R1 FE EXT_GND R6 + 3,3 V +9 - 30 V DC SMBJ30 CA R3 C1 C2 47 nF 4,7 nF R1 SMBJ30 CA SMBJ30 CA + C3 C4 220 µF 10 µF MIC2198 R5 47 µH R5 and R5 : EPCOS SIMID B82432-T1473-K, max. 340 mA GND Figure 105: Power Supply Filter 5.2.4 Reset Lines As already mentioned in chapter 3.4, reset signal lines should be kept as short as possible and should be equipped with a 1nF ceramic capacitor (connected to the reset signal and ground), located close to the netX reset input pin, to reduce the risk of undesired resets due to noise or electrostatic discharge. netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 General Design Considerations 5.2.5 147/158 Clock Circuits Any oscillator pins on the netX chips are located on outer BGA ball rings, allowing to keep the traces to a quartz crystal as short as possible. The following picture shows a recommendation for placing and routing the oscillator components: netX Figure 106: Oscillator Circuit with Ground Shield 5.2.6 Ethernet Interface When routing the two signal pairs TXP/TXN and RXP/RXN of each netX Ethernet channel, some special requirements need to be considered: • Each signal pair must be routed as a separate pair of traces which should be kept as short as possible (place magnetics and termination components as close to the netX as possible). • Traces of a pair must be routed adjacent to each other, with constant spacing and equal length. • The distance between signal pairs should be at least 5 times the spacing of the pair traces. • Traces must be impedance controlled, maintaining a differential impedance of 100 Ohm. • Minimize layer changes. If a layer change is inevitable, change layer with both traces at equal distance from start of trace and avoid changing to layers that use a different reference plane. • Avoid connectors in the signal traces; the traces should begin and end on the same PCB. If a connector is inevitable, use impedance controlled connectors to minimize any discontinuities in trace impedance. • Area where Ethernet signals are routed should be free from any other signals in adjacent layers (use only layers that are separated from the Ethernet signal layer(s) by a power or ground plane, when routing other signals in the Ethernet area). • Use the schematic from chapter 3.10.1 along with the recommended components. The following pictures show two examples of setups that keep the differential impedance of the signal pair around 100 Ohm: netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 General Design Considerations 148/158 112 µm 35 µm a) Edge-Coupled Surface Micro strip = 4.2 r 150µm (6 mil) d~ 98 150µm (6 mil) 150µm (6 mil) Figure 107: Edge-Coupled Sourface Micro Strip To improve shielding, the Ethernet traces can be routed on an inner layer, using part of the top layer as shield: b) Edge-Coupled Offset Strip line netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 220 µm 149/158 r= 4.2 365 µm 35 µm General Design Considerations r= 4.2 150µm (6 mil) d~ 96 100µm (4 mil) 100µm (4 mil) Figure 108:Edge-Coupled Offset Strip Line 5.2.7 Memory Bus When connecting SDRAM and/or parallel FLASH/SRAM etc., route the connection in a bus structure (no tree) with the bus starting at the netX, as shown in the following picture. The bus should be as short as possible and the length of the SDRAM clock signal trace should match the length of the longest SDRAM signal trace. Figure 109: netX Memory Bus 5.2.8 Planes When routing signal lines, make sure, they run over an appropriate return path (power or ground plane), that is contiguous, not more than 2 layers away and not interrupted by large gaps, as this always increases emission. When splitting planes can not be avoided, keep traces well within the plane area and do not route at the edge or even outside of the plane, as shown below: netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 General Design Considerations 150/158 Figure 110: Routibg Example netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 General Design Considerations 5.3 151/158 Vias and Traces under the netX100/500 Using a PBGA package, the netX requires small traces and vias on the PCB. However, as a result of the proper chip pinout design, four layers and 0.15 mm traces respectively 0.2 mm through whole vias are sufficient for most applications which can hence be realized by inexpensive standard printed circuit board technology. t w c g v e p Figure 111: Vias and Traces under netX100/500 Top and Bottom Side Dimension Description mm mil c Clearance 0,15 6 e Pitch 1,00 39.37 g Grid 0.15 6 p Pad 0,45 18 t Trace Width 0.15 6 v Via Diameter 0,60 24 w Drill Hole 0,20 8 PCB max. width 2,00 79 Table 41: Dimension of Printed Circuit Board Design Note: Vias within the chip footprint area should be exactly centered between the pins to avoid possible soldering problems during manufacturing! netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Reference Section 6 152/158 Reference Section The following chapters list some key components for netX100/500 designs that have been successfully evaluated by Hilscher and, where applicable, are supported by Hilscher tools (status of January 2012). 6.1 Crystals Use Part Number Manufacturer System clock CS10-25000MAGJ-UT Citizen Real Time Clock Q0.032768-JTX520-12.5-20T1-LF Jauch Quartz GmbH Table 42: Crystal Reference 6.2 Memory Components SPI FLASH Manufacturer Size Type ATMEL 2MB AT25DF161 9 - - 128kB AT25F1024A 9 - - 64kB AT25F512 - - 9 64kB AT25F512A - - 9 2MB AT26DF161 9 - - 2MB AT26DF161A 9 - - 4MB AT26DF321 9 - - 128kB AT45DB011B 9 9 9 256kB AT45DB021B 9 9 9 512kB AT45DB041B 9 9 9 1MB AT45DB081B 9 9 9 1MB AT45DB081D 9 9 9 2MB AT45DB161B 9 9 9 2MB AT45DB161D 9 9 9 4MB AT45DB321B 9 9 9 4MB AT45DB321C 9 9 9 4MB AT45DB321D 9 9 9 8MB AT45DB642D 9 9 91) EON 4MB EN25P32 9 - - Macronix 2MB MX25L1605D 9 - - 4MB MX25L3205D 9 - - 8MB MX25L6405D 9 - - 128kB PM25LV010 9 - - 64kB PM25LV512 9 - - 512kB M25P40 9 - - 64kB SA25F005 9 9 - 128kB SA25F010 9 9 - 512kB SA25F020 9 9 - 128kB M25P10VP 9 - - PMC Saifun ST Bootwizard netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public 2nd Stage rcX © Hilscher, 2008-2012 Reference Section Manufacturer ST SST 153/158 Size Type 4MB M25P32 9 9 - 8MB M25P64 9 - - 1MB M25PE80 9 9 9 2MB M45PE16 9 9 9 256kB M45PE20 9 - - 512kB M45PE40 9 9 9 1MB M45PE80 9 9 9 256kB SST25LF20A 9 - - 512kB SST25LF40A 9 - - 1MB SST25LF80A 9 - - 128kB SST25VF010 9 - - 128kB SST25VF010A 9 - - 256kB SST25VF020 9 - - 512kB SST25VF040 9 - - 64kB SST25VF512 9 - - 64kB SST25VF512A 9 - - CFI ParFlashes 9 9 - 2MB S25FL016A 9 - - 4MB S25FL032A 9 - - CFI ParFlashes 9 9 - 4MB W25P32 - - 9 2MB W25Q16 9 9 - 4MB W25Q32 9 9 9 1MB W25Q80 9 9 - 4MB W25X32 9 - - 128kB NX25P10 9 - - 256kB NX25P20 9 - - 512kb NX25P40 9 - - Spansion Strata Winbond Nymonix Bootwizard 2nd Stage rcX Table 43: Memory Component Reference SPI FLASH 1) Is not detected using the autodetect function. Parameters have to be entered in config file. Parallel Flash Manufacturer Size Part Number Spansion 16MB S29GL128P90TFIR1 32MB GL256N10FFI01 Table 44: Memory Component Reference Parallel FLASH netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Reference Section 154/158 SDRAM Manufacturer Size Part Number ISSI 8MB IS42S32200C1 (32Bit) 32MB IS42S32800B (32Bit) 64MB IS42S32160B (32Bit) 8MB MT48LC2M32B2 (32Bit) 16MB MT48LC4M32B2 (32Bit) 32MB MT48LC8M32B2 (32Bit) 64MB MT48LC16M32 (16Bit) Micron Table 45: Memory Component Reference SDRAM netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Reference Section 155/158 Appendix 6.3 List of Tables Table 1: BOM Basic Circuit Page 1................................................................................................................................... 23 Table 2: BOM Basic Circuit Page 2................................................................................................................................... 23 Table 3: BOM Basic Circuit Page 3................................................................................................................................... 24 Table 4: BOM Basic Circuit Page 4................................................................................................................................... 24 Table 5: BOM Ethernet TP Two Channel .......................................................................................................................... 26 Table 6: BOM Ethernet TP Single Channel....................................................................................................................... 28 Table 7: BOM Fiber Optic Page 1 ..................................................................................................................................... 31 Table 8: BOM Fiber Optic Page 2 ..................................................................................................................................... 32 Table 9: BOM AS-Interface Circuit .................................................................................................................................... 34 Table 10: BOM CANopen Circuit ...................................................................................................................................... 36 Table 11: BOM CC-Link Circuit ......................................................................................................................................... 38 Table 12: BOM CompoNet Circuit..................................................................................................................................... 40 Table 13: Optional BOM CompoNet Circuit....................................................................................................................... 40 Table 14: BOM DeviceNet Circuit ..................................................................................................................................... 42 Table 15: BOM PROFIBUS Circuit.................................................................................................................................... 44 Table 16: BOM MMC/SD Card Circuit............................................................................................................................... 46 Table 17: BOM microSD Circuit ........................................................................................................................................ 46 Table 18: BOM UART Ù RS232....................................................................................................................................... 48 Table 19: BOM USB Device Circuit................................................................................................................................... 50 Table 20: BOM ETM Circuit .............................................................................................................................................. 54 Table 21: BOM LCD Interface Circuit ................................................................................................................................ 57 Table 22: BOM Touch Panel Circuit.................................................................................................................................. 57 Table 23: List of Resources – rcX OS ............................................................................................................................... 59 Table 24: List of Resources – 3rd Party OS ....................................................................................................................... 60 Table 25: FLASH Sizes for Hilscher Stacks ...................................................................................................................... 61 Table 26: RDY/RUN LED Status....................................................................................................................................... 62 Table 27: ETM Signals ...................................................................................................................................................... 71 Table 28: netX100/500 Boundary Scan MMIO/GPIO Signals ........................................................................................... 73 Table 29: MMC/SD Card Insertion Signal ......................................................................................................................... 75 Table 30: Function Table of 16 Bit Decode Logic.............................................................................................................. 85 Table 31: netX DPM IntelTM Type Interface Circuits (2)..................................................................................................... 86 Table 32: Additional USB Signals ................................................................................................................................... 100 Table 33: Ethernet Circuit Component Specification....................................................................................................... 103 Table 34: Fiber Optic Ethernet Circuit Component Specification .................................................................................... 106 Table 35: Fiber Optic Ethernet Circuit Component Specification (AC-Termination) ........................................................ 107 Table 36: Status LEDs for Ethernet Ports ....................................................................................................................... 114 Table 37: Additional RTE Sync Signals netX100/500 ..................................................................................................... 115 Table 38: Status LEDs for Real Time Ethernet Applications ........................................................................................... 116 Table 39: Status LEDs for Fieldbus Ports ....................................................................................................................... 126 Table 40: Fieldbus Status LED Colors ............................................................................................................................ 126 Table 41: Dimension of Printed Circuit Board Design ..................................................................................................... 151 Table 42: Crystal Reference............................................................................................................................................ 152 Table 43: Memory Component Reference SPI FLASH ................................................................................................... 153 Table 44: Memory Component Reference Parallel FLASH ............................................................................................. 153 Table 45: Memory Component Reference SDRAM ........................................................................................................ 154 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Reference Section 6.4 156/158 List of Figures Figure 1: netX100/500 RDY/RUN Basic Circuit................................................................................................................... 7 Figure 2: netX100/500 SPI Flash ........................................................................................................................................ 8 Figure 3: netX100/500 Secure Memory Basic Circuit.......................................................................................................... 8 Figure 4: netX100/500 System Oscillator Circuit................................................................................................................. 9 Figure 5: netX100/500 RTC Not Used in Basic Circuit ........................................................................................................ 9 Figure 6: netX100/500 Reset Circuit ................................................................................................................................. 10 Figure 7: netX100/500 USB DOWN Stream Port (Device Mode)...................................................................................... 10 Figure 8: netX100/500 UART0 Unused............................................................................................................................. 11 Figure 9: Unused ADC Basic Circuit ................................................................................................................................. 11 Figure 10: netX100/500 Connection of 8MB SDRAM ....................................................................................................... 12 Figure 11: netX100/500 Ethernet Not Used ...................................................................................................................... 13 Figure 12: Unused Host Interface ..................................................................................................................................... 15 Figure 13: +3.3 V Power Supply Standard Circuit ............................................................................................................. 16 Figure 14: 1.5 V Core Voltage Regulator .......................................................................................................................... 16 Figure 15: netX100/500 Power Connection ...................................................................................................................... 17 Figure 16: netX100/500 Basic Circuit RDY/RUN USB SEC-MEM SPI-FLASH ................................................................. 18 Figure 17: netX100/500 Basic Circuit SDRAM .................................................................................................................. 19 Figure 18: netX100/500 Basic Circuit ADC, Host Interface, PHY, RTC ............................................................................ 20 Figure 19: netX100/500 Basic Circuit Power Supply......................................................................................................... 21 Figure 20: netX100/500 Basic Circuit Unused netX Parts ................................................................................................. 22 Figure 21: Ethernet TP Dual Channel Circuit .................................................................................................................... 25 Figure 22: Ethernet TP Single Channel Circuit.................................................................................................................. 27 Figure 23: Fiber Optic Circuit on netX100/500 Side .......................................................................................................... 29 Figure 24: Fiber Optic Circuit on AFBR-5978Z Side ......................................................................................................... 30 Figure 25: AS-Interface Circuit .......................................................................................................................................... 33 Figure 26: CANopen Circuit .............................................................................................................................................. 35 Figure 27: CC-Link Circuit ................................................................................................................................................. 37 Figure 28: CompoNet Circuit............................................................................................................................................. 39 Figure 29: DeviceNet Circuit ............................................................................................................................................. 41 Figure 30: PROFIBUS Circuit............................................................................................................................................ 43 Figure 31: netX100/500 MMC/SD-Card SPI Circuit .......................................................................................................... 45 Figure 32: UART Ù RS232 Circuit ................................................................................................................................... 47 Figure 33: USB Device Mode Circuit................................................................................................................................. 49 Figure 34: USB Host Mode Circuit .................................................................................................................................... 51 Figure 35: BOM USB Host Mode Circuit ........................................................................................................................... 52 Figure 36: ETM Circuit ...................................................................................................................................................... 53 Figure 37: LCD Interface Circuit........................................................................................................................................ 55 Figure 38: Touch Panel Circuit.......................................................................................................................................... 56 Figure 39: netX100/netX500 RDY/RUN Circuit ................................................................................................................. 63 Figure 40: Sample Schematic, netX100/500 Secure Memory........................................................................................... 65 Figure 41: netX100/500 System Oscillator Circuit............................................................................................................. 66 Figure 42: netX500 RTC Circuits ...................................................................................................................................... 67 Figure 43: netX100/500 RTC Unused ............................................................................................................................... 68 Figure 44:netX Reset Circuits ........................................................................................................................................... 69 Figure 45: netX JTAG Circuits........................................................................................................................................... 70 Figure 46: netX100/500 Boundary Scan JTAG/TEST Signals .......................................................................................... 72 Figure 47: netX100/500 SPI Flash .................................................................................................................................... 75 Figure 48: netx100/500 MMC/SD Card ............................................................................................................................. 75 Figure 49: Solution, if SD Card Disturbs SPI Data Transmission from FLASH ................................................................. 76 Figure 50: netX FLASH - Address Line A0 for Low/High Byte Selection........................................................................... 78 Figure 51: netX FLASH - A0 as the LSB of a Word Address............................................................................................. 79 Figure 52:netX SDRAM 1 *16 Bit, 1 * 32 Bit, 2 * 16 Bit ..................................................................................................... 82 Figure 53:netX SDRAM 4 * 8 Bit ....................................................................................................................................... 83 Figure 54: netX100/500 VDDH Pins.................................................................................................................................. 84 Figure 55: netX DPM IntelTM Type Interface Circuits (1) ................................................................................................... 85 Figure 56: netX DPM MotorolaTM Type Interface Circuits.................................................................................................. 86 Figure 57: Texas Instruments TMS320x2833xTM, 16 Bit, Non Multiplexed ....................................................................... 87 Figure 58: netX DPM IntelTM Type Circuits, Multiplexed.................................................................................................... 88 Figure 59: netX DPM MotorolaTM Type Interface Circuit, Multiplexed ............................................................................... 88 Figure 60: netX ISA Bus Interface Circuit.......................................................................................................................... 89 Figure 61: netX Internal Chip Select Generator Circuits ................................................................................................... 91 Figure 62: netX Extension Bus IntelTM Type Interface Circuit 8Bit, non Multiplex ............................................................. 93 Figure 63: netX Extension Bus IntelTM type Interface Circuit 16Bit, non Multiplex............................................................. 94 Figure 64: netX DPM MotorolaTM Type Interface Circuits, non Multiplex........................................................................... 94 Figure 65: netX DPM IntelTM Type Interface Circuit, Multiplexed....................................................................................... 95 Figure 66: netX Extension Bus MotorolaTM Interface Circuit, Multiplexed ......................................................................... 96 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Reference Section 157/158 Figure 67: netX100/500 UART0 ........................................................................................................................................ 97 Figure 68: netX100/500 UART0 Unused........................................................................................................................... 97 Figure 69: netX100/500 USB DOWNstream Port (Device Mode) ..................................................................................... 99 Figure 70: netX100/500 USB DOWNstream Port (Device Mode), Advanced Circuit ...................................................... 100 Figure 71: netX100/500 USB UPstream Port (Host Mode) ............................................................................................. 101 Figure 72: netX100/500 2 Channel Ethernet Circuit (Twisted Pair)................................................................................. 102 Figure 73: netX Single Channel Ethernet Circuit (Twisted Pair)...................................................................................... 104 Figure 74: netX100/500 Ethernet Circuit (Fiber Optic) .................................................................................................... 105 Figure 75: netX100/500 Ethernet Circuit (Fiber Optic) .................................................................................................... 107 Figure 76: netX Ethernet Circuit (Fiber Optic), Component Placement........................................................................... 109 Figure 77: netX Ethernet Circuit (Fiber Optic), Component Placement with AC-Termination ......................................... 110 Figure 78: netX100/500 I2C Interface Fiber Optic Transceivers ...................................................................................... 111 Figure 79: netX100/500 Ethernet Circuit (PHYs Not Used)............................................................................................. 113 Figure 80: netX100/500 Ethernet Status LED Circuit ...................................................................................................... 114 Figure 81: netX RTE Status LED Schematic................................................................................................................... 116 Figure 82: netX100/500 Fieldbus Interface ..................................................................................................................... 119 Figure 83: Basic Circuit for netX AS-Interface................................................................................................................. 120 Figure 84: Basic Circuit of netX CANopen Interface ....................................................................................................... 121 Figure 85: Basic Circuit for netX CC-Link Interface......................................................................................................... 122 Figure 86: Basic Circuit for netX CompoNet Interface..................................................................................................... 123 Figure 87: Basic Circuit for netX DeviceNet Interface ..................................................................................................... 124 Figure 88: Basic Circuit for netX PROFIBUS Interface ................................................................................................... 125 Figure 89: ADC Circuit .................................................................................................................................................... 127 Figure 90: ADC Circuit, One Channel Used .................................................................................................................... 128 Figure 91: ADC Circuit, ADCs Unused............................................................................................................................ 129 Figure 92: PWM/Encoder/xMAC/xPAC Resource Sharing ............................................................................................. 130 Figure 93: Encoder Circuit Example................................................................................................................................ 132 Figure 94: LCD-Backlight-PWM; RC-Filter; Windows CE ............................................................................................... 134 Figure 95: Touch Panel Circuit........................................................................................................................................ 135 Figure 96: netX Core Voltage Regulator ......................................................................................................................... 138 Figure 97: Alternative Core Voltage Regulator................................................................................................................ 139 Figure 98: netX +3V3 Supply .......................................................................................................................................... 139 Figure 99: netX +5V Supply ............................................................................................................................................ 140 Figure 102: Approved netX PCB Layer Stack ................................................................................................................. 144 Figure 103: netX100/500 Decoupling Caps .................................................................................................................... 145 Figure 104: netX100/500 Decoupling Caps Vias and Inner Plane for VDD-IO and VDD-CORE..................................... 145 Figure 105: Power Supply Filter ...................................................................................................................................... 146 Figure 106: Oscillator Circuit with Ground Shield............................................................................................................ 147 Figure 107: Edge-Coupled Sourface Micro Strip............................................................................................................. 148 Figure 108:Edge-Coupled Offset Strip Line..................................................................................................................... 149 Figure 109: netX Memory Bus......................................................................................................................................... 149 Figure 110: Routibg Example.......................................................................................................................................... 150 Figure 111: Vias and Traces under netX100/500 Top and Bottom Side ......................................................................... 151 netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012 Contacts 7 158/158 Contacts Headquarters Germany Hilscher Gesellschaft für Systemautomation mbH Rheinstrasse 15 65795 Hattersheim Phone: +49 (0) 6190 9907-0 Fax: +49 (0) 6190 9907-50 E-Mail: [email protected] Support Phone: +49 (0) 6190 9907-99 E-Mail: [email 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Ltd. 200010 Shanghai Phone: +86 (0) 21-6355-5161 E-Mail: [email protected] Hilscher Japan KK Tokyo, 160-0022 Phone: +81 (0) 3-5362-0521 E-Mail: [email protected] Support Support Phone: +86 (0) 21-6355-5161 E-Mail: [email protected] Phone: +81 (0) 3-5362-0521 E-Mail: [email protected] France Korea Hilscher France S.a.r.l. 69500 Bron Phone: +33 (0) 4 72 37 98 40 E-Mail: [email protected] Hilscher Korea Inc. Suwon, Gyeonggi, 443-734 Phone: +82 (0) 31-695-5515 E-Mail: [email protected] Support Phone: +33 (0) 4 72 37 98 40 E-Mail: [email protected] India Hilscher India Pvt. Ltd. New Delhi - 110 065 Phone: +91 11 43055431 E-Mail: [email protected] Switzerland Hilscher Swiss GmbH 4500 Solothurn Phone: +41 (0) 32 623 6633 E-Mail: [email protected] Support Phone: +49 (0) 6190 9907-99 E-Mail: [email protected] Italy USA Hilscher Italia S.r.l. 20090 Vimodrone (MI) Phone: +39 02 25007068 E-Mail: [email protected] Hilscher North America, Inc. Lisle, IL 60532 Phone: +1 630-505-5301 E-Mail: [email protected] Support Support Phone: +39 02 25007068 E-Mail: [email protected] Phone: +1 630-505-5301 E-Mail: [email protected] netX Design-In Guide | netX 100/500 DOC081106AN02EN | Revision 2 | English | 2012-10 | Released | Public © Hilscher, 2008-2012