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16. Registers
Register access transactions are limited to a maximum of 8 bytes. The selected bytes
are changed during writes. All bytes are returned on reads.
Refer to “Data Alignment” on page 42 for more information on setting the register
access size from 4 bytes (default) to 8 bytes.
Bursting to the registers is not supported.
16.2.3.1
Termination
When a register access exceeds 8 bytes, or the external master attempts to burst to
the registers, the PB Slave asserts Processor Bus Transfer Error Acknowledge
(PB_TEA_). This signal indicates a bus error and terminates the transaction.
16.2.3.2
SDRAM Memory Images
SDRAM memory images route memory mapped transactions to SDRAM. These
images never assert PB_ARTRY_. Any valid processor (60x) bus transaction is
supported, including MPC8260 extended cycles.
16.2.3.3
FLASH/ROM Memory Images
FLASH/ROM memory images route memory mapped transactions to EEPROM,
Flash, SRAM and the peripheral bus. Any valid processor (60x) bus cycle can be
mapped to any size of EEPROM device, with PowerPro buffering the cycle
information and performing multiple FLASH/ROM transactions as required.
When enabled, PB_ARTRY_ can be asserted by PowerPro during reads or writes
when the FLASH/ROM Interface is busy processing a slow cycle.
16.3
Register Reset
The register space contains a single reset domain: the Processor Bus Interface
registers.
Registers are configured after reset through the Configuration Master or
Configuration Slave configuration cycle. Refer to “Power-up” on page 151 for more
information.
16.4
Register Descriptions
The PowerPro register space can be divided into the following groups:
•
Processor Bus
•
SDRAM
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