Download M3 32-bit MCU User Manual

GD32F10x User Manual
The low speed external crystal or ceramic resonator oscillator, which has a frequency of
32,768 Hz, produces a low power but highly accurate clock source for the Real Time Clock
circuit. The LSE oscillator can be switched on or off using the LSEEN bit in the Backup
Domain Control Register RCC_BDCR. The LSESTB flag in the Backup Domain Control
Register RCC_BDCR will indicate if the LSE clock is stable. An interrupt can be generated if
the related interrupt enable bit, LSESTBIE, in the Global Clock Interrupt Register RCC_GCIR
is set when the LSE becomes stable.
Select external clock bypass mode by setting the LSEBPS and LSEEN bits in the Backup
Domain Control Register RCC_BDCR. In bypass mode, the external clock must be provided
to the OSC32_IN pin. The CK_LSE is equal to the external clock which drives the OSC32_IN
pin.
Low Speed Internal RC Oscillator (LSI)
The low speed internal RC oscillator has a frequency of about 40 kHz and is a low power
clock source for the Real Time Clock circuit or the Independent Watchdog Timer. The LSI
offers a low cost clock source as no external components are required. The LSI RC oscillator
can be switched on or off by using the LSIEN bit in the Global Control/Status Register,
RCC_GCSR. The LSISTB flag in the Global Control/Status Register RCC_GCSR will
indicate if the LSI clock is stable. An interrupt can be generated if the related interrupt enable
bit LSISTBIE in the Global Clock Interrupt Register RCC_GCIR is set when the LSI becomes
stable.
System Clock (CK_SYS) Selection
After the system reset, the default CK_SYS source will be HSI and can be switched to HSE
or PLL by changing the System Clock Switch bits, SCS, in the Global Clock configuration
register, RCC_GCFGR. When the SCS value is changed, the CK_SYS will continue to
operate using the original clock source until the target clock source is stable. When a clock
source is used directly by the CK_SYS or the PLL, it is not possible to stop it.
HSE Clock Monitor (CKM)
The HSE clock monitor function is enabled by the HSE Clock Monitor Enable bit, CKMEN, in
the Global Clock Control Register, RCC_GCCR. This function should be enabled after the
HSE start-up delay and disabled when the HSE is stopped. Once the HSE failure is detected,
the HSE will be automatically disabled. The HSE Clock Stuck Flag, CKMF, in the Global
Clock Interrupt Register, RCC_GCIR, will be set and the HSE failure event will be generated.
This failure interrupt is connected to the Non-Maskable Interrupt, NMI, of the Cortex-M3. If
the HSE is selected as the clock source of CK_SYS or PLL, the HSE failure will force the
CK_SYS source to HSI and the PLL will be disabled automatically.
Clock Output Capability
The output clock capability can be ranging from 32 kHz to 54 MHz. There are several clock
signals can be selected via the CKOUT Clock Source Selection bits, CKOUTSRC, in the
Global Clock Configuration Register, RCC_GCFGR. The corresponding GPIO pin should be
105