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Download M3 32-bit MCU User Manual
Transcript
GD32F10x User Manual 0: No window watchdog reset generated 1: Window watchdog reset generated 29 IWDGRSTF Independent watchdog timer reset flag Set by hardware when an independent watchdog timer generated. Reset by writing 1 to the RSTFC bit. 0: No Independent watchdog timer reset generated 1: Independent Watchdog timer reset generated 28 SWRSTF Software reset flag Set by hardware when a software reset generated. Reset by writing 1 to the RSTFC bit. 0: No software reset generated 1: Software reset generated 27 POPDRSTF Power On/Power Down reset flag Set by hardware when a Power On/Power Down reset generated. Reset by writing 1 to the RSTFC bit. 0: No Power On/Power Down reset generated 1: Power On/Power Down reset generated 26 EPRSTF External PIN reset flag Set by hardware when a External PIN generated. Reset by writing 1 to the RSTFC bit. 0: No External PIN reset generated 1: External PIN reset generated 25 Reserved must be kept at reset value. 24 RSTFC Reset flag clear This bit is set by software to clear all reset flags. 0: Not clear reset flags 1: Clear reset flags 23:2 Reserved must be kept at reset value. 1 LSISTB LSI stabilization Set by hardware to indicate if the LSI output clock is stable and ready for use. 0: LSI is not stable 1: LSI is stable 0 LSIEN LSI enable Set and reset by software. 0: Disable LSI 130
