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I N T R O D U C T I O N T O T H E S O F T W A R E T O O L S FPGA C FPGA C FPGA C FPGA C FPGA C FPGA C 0x28000010 0x28000011 0x28100001 0x28100002 0x28100003 0x28100004 LED_OE LED_OUT CLK_COUNTER CLK_COUNTER CLK_COUNTER CLK_COUNTER Controls LED output enables Controls LED outputs Contains contents of ACLK counter Contains contents of BCLK counter Contains contents of DCLK counter Contains contents of SYSCLK counte FPGA C FPGA C FPGA C FPGA C FPGA C 0x28000001 0x28000003 0x28000005 0x28000007 0x28000008 DDR2HIADDR HIADDRSIZE DDR2SIZEHIADDR DDR2TAPCNT0 DDR2TAPCNT1 upper address bits for DDR2 interface number of bits in DDR2HIADDR The size of the DDR2 module. Current IDELAY values of DDR2… …interface 2.1 Using the Reference Design 2.1.1 Built-In RocketIO test From the AETest main menu, select option 4, MGT Menu. The MGT test sends a repeating test pattern out all of the RocketIO transmit pairs, and compares the input of each RocketIO channel to that pattern. To run the test, you must loop back each RocketIO pair. DN8000K10PCIE User Guide www.dinigroup.com 99
