Download User`s Manual

2.3.1
Jtag
Jtag is the only configuration method on the DN8000K10PCIE that does not use the Virtex 4
SelectMap configuration interface. When programming the user FPGAs over a JTAG cable
plugged into J13, the DN8000K10PCIE configuration circuitry is not used.
A JTAG connection is required to use some Xilinx configuration tools like ChipScope, and
readback from Impact. Configuration over JTAG is slower than SelectMap. You can still use the
SmartMedia or USB interfaces to control clock settings if you plan to configure through JTAG.
To configure using JTAG, we recommend using Xilinx Parallel cable IV, or Xilinx platform
USB cable. The Xilinx program. You should set the configuration speed of your JTAG cable to
4Mhz or below.
FPGA JTAG (Cable IV)
+2.5V +2.5V
R261R264R265R266
1K 1K 1K 1K
J13
1
3
5
7
9
11
13
2
4
6
8
10
12
14
JTAG_FPGA_TMS
RJTAG_FPGA_TCK
JTAG_FPGA_TDO
JTAG_FPGA_TDI
JTAG_FPGA_TMS
JTAG_FPGA_TDO
JTAG_FPGA_TDI
JTAG_FPGA_INITn
JTAG_FPGA_INITn
87332-1420
R263
1K
Figure 25 FPGA JTAG Header
The JTAG signals TMS is bussed to all three Virtex 4 FPGAs. TDO connects to FPGA A, the
TDO of FPGA is connected to TDI of FPGA B, the TDO of FPGA B connects to the TDI of
FPGA C and TDO of FPGA C is connected to the TDI of J13. TCK is buffered and passed to
each FPGA in a point-to-point fassion.
Note: These signals should be
matched length.
JTAG Clock Buffer
U32
1
2
6
10
17
BUFIN
GND
GND
GND
GND
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
VDD
VDD
VDD
VDD
3
5
7
9
11
12
14
16
18
19
4
8
15
20
RFPGA_TCK_A
RFPGA_TCK_B
RFPGA_TCK_C
R278
R279
R271
33R JTAG_FPGA_TCKA
33R JTAG_FPGA_TCKB
33R JTAG_FPGA_TCKC
JTAG_FPGA_TCKA
JTAG_FPGA_TCKB
JTAG_FPGA_TCKC
+2.5V
FPGA_JTAG_AVDD
C851
0.1uF
+
CY2CC9100C
C826
10uF
10V
20%
TANT
FB100
C914
0.1uF
Figure 26 TCK buffer
The INITn signal is not used.
DN8000K10PCIE User Guide
www.dinigroup.com
48