1
Download UM10316
Transcript
D D R R R R R D D D D R R D A FT R R R Activity-detection register for normal PLL output FT FT D D R A D R A Activity-detection register for crystal -oscillator output LP_OSC_PRESEN R T (CGU0) or BASE_ICLK1_CLK_ PRESENT (CGU1) 1* Clock present 0 Clock not present 1* Clock present 0 Clock not present Activity-detection register for LP_OSC 5.3 Crystal-oscillator status register (CGU0) The register XTAL_OSC_STATUS reflects the status bits for the crystal oscillator. Table 17. XTAL_OSC_STATUS register bit description (XTAL_OSC_STATUS, address 0xFFFF 801C) * = reset value Bit Symbol Access Value Description 31 to 3 reserved R Reserved 2 HF R 1 0 BYPASS ENABLE - Oscillator HF pin 1* Oscillator high-frequency mode (crystal or external clock source above 10 MHz) 0 Oscillator low-frequency mode (crystal or external clock source below 20 MHz) R Configure crystal operation or external clock input pin XIN_OSC 0 Operation with crystal connected 1* Bypass mode. Use this mode when an external clock source is used instead of a crystal R Oscillator-pad enable 0 Power-down 1* Enable 5.4 Crystal oscillator control register (CGU0) The register XTAL_OSC_CONTROL contains the control bits for the crystal oscillator. Following a change of ENABLE bit in XTAL_OSC_CONTROL register requires a read in XTAL_OSC_STATUS to confirm ENABLE bit is indeed changed. UM10316_0 User manual © NXP B.V. 2008. All rights reserved. Rev. 00.06 — 17 December 2008 FT 0 A PLL_PRESENT A R 2 XTAL_PRESENT R (CGU0) or BASE_ICLK0_CLK_ PRESENT (CGU1) F D D Description 1 A FT FT A A R R D D D Access Value Clock not present R R FT FT A A R R D D D Symbol 0 FT FT FT FT Bit Clock present A A A A R R D D D RDET register bit description (RDET, address 0xFFFF 8018 (CGU0) or 0xFFFF B018 (CGU1)) …continued * = reset value 1* FT FT FT FT FT UM10316 Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 16. A A A A A NXP Semiconductors 37 of 571
