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D D R R R R R D D D D R R R A FT R A F FT FT A A R R D D D D FT FT A A R R D Master: sending, Slave: receiving D R FT FT A A R R D D D Master: sending, Slave: receiving FT FT FT FT Response fields A A A A R R D D D Header fields FT FT FT FT FT UM10316 Chapter 22: LPC29xx LIN 0/1 Case 1: DD = 0 A A A A A NXP Semiconductors D D R A FT Transmit message complete interrupt D R A Case 2: DD = 1 Master: sending, Slave: receiving Master: sending, Slave: receiving Receive message complete interrupt Case 1 TS Cleared with transmit message complete or bit-error or line clamped error condition RS Case 2 TS RS Cleared with receive message complete or bit-error or line clamped error condition or time-out condition MR HS IS = MBA Released/Idle with transmit message complete or receive message complete or bit-error or line clamped error condition or time-out condition 001aaa173 Fig 90. LIN master-controller status-flag handling Table 308. LIN master-controller status register bit description * = reset value Access Value Description 31 to 10 reserved Bit Symbol R Reserved; read as logic 0 9 R TTL - TXD line level 1* 0 8 7 RLL reserved R R The current TXD line level is dominant The current TXD line level is recessive RXD line level. 1* The current RXD line level is dominant 0 The current RXD line level is recessive - Reserved; read as logic 0 UM10316_0 User manual © NXP B.V. 2008. All rights reserved. Rev. 00.06 — 17 December 2008 370 of 571
